LM3S310 Data Sheet
October 6, 2006
7
Preliminary
List of Figures
Figure 1-1.
Stellaris High-Level Block Diagram ........................................................................................... 23
Figure 1-2.
LM3S310 Controller System-Level Block Diagram ................................................................... 29
Figure 2-1.
CPU Block Diagram .................................................................................................................. 31
Figure 2-2.
TPIU Block Diagram .................................................................................................................. 32
Figure 5-1.
JTAG Module Block Diagram .................................................................................................... 39
Figure 5-2.
Test Access Port State Machine ............................................................................................... 42
Figure 5-3.
IDCODE Register Format.......................................................................................................... 46
Figure 5-4.
BYPASS Register Format ......................................................................................................... 46
Figure 5-5.
Boundary Scan Register Format ............................................................................................... 47
Figure 6-1.
External Circuitry to Extend Reset............................................................................................. 49
Figure 6-2.
Main Clock Tree ........................................................................................................................ 52
Figure 7-1.
Flash Block Diagram ................................................................................................................. 90
Figure 8-1.
GPIO Module Block Diagram .................................................................................................. 105
Figure 8-2.
GPIO Port Block Diagram........................................................................................................ 106
Figure 8-3.
GPIODATA Write Example...................................................................................................... 107
Figure 8-4.
GPIODATA Read Example ..................................................................................................... 107
Figure 9-1.
GPTM Module Block Diagram ................................................................................................. 143
Figure 9-2.
16-Bit Input Edge Count Mode Example ................................................................................. 147
Figure 9-3.
16-Bit Input Edge Time Mode Example...................................................................................148
Figure 9-4.
16-Bit PWM Mode Example .................................................................................................... 149
Figure 10-1.
WDT Module Block Diagram ................................................................................................... 174
Figure 11-1.
UART Module Block Diagram.................................................................................................. 198
Figure 11-2.
UART Character Frame........................................................................................................... 199
Figure 12-1.
SSI Module Block Diagram...................................................................................................... 233
Figure 12-2.
TI Synchronous Serial Frame Format (Single Transfer).......................................................... 235
Figure 12-3.
TI Synchronous Serial Frame Format (Continuous Transfer) ................................................. 236
Figure 12-4.
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................................... 237
Figure 12-5.
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................................. 237
Figure 12-6.
Freescale SPI Frame Format with SPO=0 and SPH=1........................................................... 238
Figure 12-7.
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0............................... 238
Figure 12-8.
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0....................... 239
Figure 12-9.
Freescale SPI Frame Format with SPO=1 and SPH=1........................................................... 239
Figure 12-10. MICROWIRE Frame Format (Single Frame)........................................................................... 240
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................................... 241
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements............................ 242
Figure 13-1.
Analog Comparator Module Block Diagram ............................................................................ 268
Figure 13-2.
Structure of Comparator Unit................................................................................................... 269
Figure 13-3.
Comparator Internal Reference Structure ............................................................................... 270
Figure 14-1.
PWM Module Block Diagram................................................................................................... 280
Figure 14-2.
PWM Count-Down Mode......................................................................................................... 281
Figure 14-3.
PWM Count-Up/Down Mode ................................................................................................... 282
Figure 14-4.
PWM Generation Example In Count-Up/Down Mode ............................................................. 282
Figure 14-5.
PWM Dead-Band Generator ................................................................................................... 283
Figure 15-1.
Pin Connection Diagram.......................................................................................................... 312
Figure 18-1.
Load Conditions....................................................................................................................... 327
Figure 18-2.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ................ 329