Figure 15-10. Master Burst RECEIVE .................................................................................................. 383
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 384
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 385
Figure 15-13. Slave Command Sequence ............................................................................................ 386
Figure 16-1.
CAN Module Block Diagram ........................................................................................... 411
Figure 16-2.
CAN Bit Time ................................................................................................................ 418
Figure 17-1.
Analog Comparator Module Block Diagram ..................................................................... 452
Figure 17-2.
Structure of Comparator Unit .......................................................................................... 453
Figure 17-3.
Comparator Internal Reference Structure ........................................................................ 454
Figure 18-1.
PWM Module Block Diagram .......................................................................................... 464
Figure 18-2.
PWM Count-Down Mode ................................................................................................ 465
Figure 18-3.
PWM Count-Up/Down Mode .......................................................................................... 466
Figure 18-4.
PWM Generation Example In Count-Up/Down Mode ....................................................... 466
Figure 18-5.
PWM Dead-Band Generator ........................................................................................... 467
Figure 19-1.
QEI Block Diagram ........................................................................................................ 501
Figure 19-2.
Quadrature Encoder and Velocity Predivider Operation .................................................... 502
Figure 20-1.
Pin Connection Diagram ................................................................................................ 517
Figure 23-1.
Load Conditions ............................................................................................................ 537
Figure 23-2.
I2C Timing ..................................................................................................................... 540
Figure 23-3.
Hibernation Module Timing ............................................................................................. 540
Figure 23-4.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 541
Figure 23-5.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 541
Figure 23-6.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 542
Figure 23-7.
JTAG Test Clock Input Timing ......................................................................................... 543
Figure 23-8.
JTAG Test Access Port (TAP) Timing .............................................................................. 543
Figure 23-9.
JTAG TRST Timing ........................................................................................................ 543
Figure 23-10. External Reset Timing (RST) .......................................................................................... 544
Figure 23-11. Power-On Reset Timing ................................................................................................. 545
Figure 23-12. Brown-Out Reset Timing ................................................................................................ 545
Figure 23-13. Software Reset Timing ................................................................................................... 545
Figure 23-14. Watchdog Reset Timing ................................................................................................. 545
Figure 24-1.
100-Pin LQFP Package .................................................................................................. 546
November 30, 2007
10
Preliminary
Table of Contents