6.1.3
Power Control ........................................................................................................................... 63
6.1.4
Clock Control ............................................................................................................................ 63
6.1.5
System Control ......................................................................................................................... 65
6.2
Initialization and Configuration ................................................................................................... 66
6.3
Register Map ............................................................................................................................ 66
6.4
Register Descriptions ................................................................................................................ 67
7
Hibernation Module .......................................................................................................... 121
7.1
Block Diagram ........................................................................................................................ 122
7.2
Functional Description ............................................................................................................. 122
7.2.1
Register Access Timing ........................................................................................................... 122
7.2.2
Clock Source .......................................................................................................................... 123
7.2.3
Battery Management ............................................................................................................... 123
7.2.4
Real-Time Clock ...................................................................................................................... 123
7.2.5
Non-Volatile Memory ............................................................................................................... 124
7.2.6
Power Control ......................................................................................................................... 124
7.2.7
Interrupts and Status ............................................................................................................... 124
7.3
Initialization and Configuration ................................................................................................. 125
7.3.1
Initialization ............................................................................................................................. 125
7.3.2
RTC Match Functionality (No Hibernation) ................................................................................ 125
7.3.3
RTC Match/Wake-Up from Hibernation ..................................................................................... 125
7.3.4
External Wake-Up from Hibernation .......................................................................................... 126
7.3.5
RTC/External Wake-Up from Hibernation .................................................................................. 126
7.4
Register Map .......................................................................................................................... 126
7.5
Register Descriptions .............................................................................................................. 127
8
Internal Memory ............................................................................................................... 140
8.1
Block Diagram ........................................................................................................................ 140
8.2
Functional Description ............................................................................................................. 140
8.2.1
SRAM Memory ........................................................................................................................ 140
8.2.2
Flash Memory ......................................................................................................................... 141
8.3
Flash Memory Initialization and Configuration ........................................................................... 142
8.3.1
Flash Programming ................................................................................................................. 142
8.3.2
Nonvolatile Register Programming ........................................................................................... 143
8.4
Register Map .......................................................................................................................... 143
8.5
Flash Register Descriptions (Flash Control Offset) ..................................................................... 144
8.6
Flash Register Descriptions (System Control Offset) .................................................................. 151
9
General-Purpose Input/Outputs (GPIOs) ....................................................................... 164
9.1
Functional Description ............................................................................................................. 164
9.1.1
Data Control ........................................................................................................................... 165
9.1.2
Interrupt Control ...................................................................................................................... 166
9.1.3
Mode Control .......................................................................................................................... 167
9.1.4
Commit Control ....................................................................................................................... 167
9.1.5
Pad Control ............................................................................................................................. 167
9.1.6
Identification ........................................................................................................................... 167
9.2
Initialization and Configuration ................................................................................................. 167
9.3
Register Map .......................................................................................................................... 169
9.4
Register Descriptions .............................................................................................................. 170
November 30, 2007
4
Preliminary
Table of Contents