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LA4128C-75TN44E датащи(PDF) 10 Page - Lattice Semiconductor

номер детали LA4128C-75TN44E
подробное описание детали  3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
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производитель  LATTICE [Lattice Semiconductor]
домашняя страница  http://www.latticesemi.com
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LA4128C-75TN44E датащи(HTML) 10 Page - Lattice Semiconductor

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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
10
Figure 8. I/O Cell
Each output supports a variety of output standards dependent on the VCCO supplied to its I/O bank. Outputs can
also be configured for open drain operation. Each input can be programmed to support a variety of standards, inde-
pendent of the VCCO supplied to its I/O bank. The I/O standards supported are:
• LVTTL
• LVCMOS 1.8
• LVCMOS 3.3
• 3.3V PCI Compatible
• LVCMOS 2.5
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down
Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both
hardware and software is such that when the device is erased or if the user does not specify, the input structure is
configured to be a Pull-up Resistor.
Each LA-ispMACH 4000V/Z automotive device I/O has an individually programmable output slew rate control bit.
Each output can be individually configured for fast slew or slow slew. The typical edge rate difference between fast
and slow slew setting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will intro-
duce fewer reflections, less noise and keep ground bounce to a minimum. For designs with short traces or well ter-
minated lines, the fast slew rate can be used to achieve the highest speed.
Global OE Generation
Most LA-ispMACH 4000V/Z automotive family devices have a 4-bit wide Global OE Bus, except the LA-ispMACH
4032V and LA-ispMACH4032Z devices that have a 2-bit wide Global OE Bus. This bus is derived from a 4-bit inter-
nal global OE PT bus and two dual purpose I/O or GOE pins. Each signal that drives the bus can optionally be
inverted.
Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a
128-macrocell device (with 16 blocks), each line of the bus is driven from 8 OE product terms. Figures 9 and 10
show a graphical representation of the global OE generation.
GOE 0
From ORP
*Global fuses
From ORP
To Macrocell
To GRP
GOE 1
GOE 2
GOE 3
VCC
VCCO
VCCO
**
*


Аналогичный номер детали - LA4128C-75TN44E

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Аналогичное описание - LA4128C-75TN44E

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