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TLC5944 датащи(PDF) 8 Page - Texas Instruments |
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TLC5944 датащи(HTML) 8 Page - Texas Instruments |
8 / 34 page TLC5944 SBVS112 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com TERMINAL FUNCTIONS TERMINAL NAME PWP RHB I/O DESCRIPTION SIN 5 2 I Serial data input for grayscale and dot correction. Serial data shift clock for GS shift register and DC shift register. Schmitt buffer input. The shift register is selected by the DCSEL pin. Data present on the SIN pin are shifted into the shift SCLK 4 1 I register selected by DCSEL with the rising edge of the SCLK pin. Data in the selected shift register are shifted to the MSB side by 1-bit synchronizing to the rising edge of SCLK. The MSB data of the selected register appears on SOUT. Data in the GS and DC shift register are moved to the respective data latch with a low-to-high XLAT 3 32 I transition of this pin. Shift register and data latch select. When DCSEL is low, SCLK/XLAT/SOUT are connected to the DCSEL 6 3 I GS shift register and data latch. When DCSEL is high, SCLK/XLAT/SOUT are connected to the DC shift register and data latch. DCSEL should not be changed while SCLK is high. Reference clock for grayscale PWM control. If BLANK is low, then each rising edge of GSCLK GSCLK 25 24 I increments the grayscale counter for PWM control. Blank (all constant current outputs off). When BLANK is high, all constant current outputs (OUT0 through OUT15) are forced off, the grayscale counter is reset to '0', and the grayscale PWM BLANK 2 31 I timing controller is initialized. When BLANK is low, all constant current outputs are controlled by the grayscale PWM timing controller. Constant current value setting. OUT0 through OUT15 sink constant current is set to the desired IREF 27 26 I/O value by connecting an external resistor between IREF and GND. Serial data output for GS, DC, and status information data (SID). This output is connected to the SOUT 24 23 O MSB of the shift register selected by DCSEL. Error output. Open-drain output. XERR goes low when LOD or TEF are set. XERR is in high XERR 23 22 O impedance when error free. Constant current output. Each output can be tied to other outputs to increase the constant OUT0 7 4 O current. OUT1 8 5 O Constant current output OUT2 9 6 O Constant current output OUT3 10 7 O Constant current output OUT4 11 8 O Constant current output OUT5 12 9 O Constant current output OUT6 13 10 O Constant current output OUT7 14 11 O Constant current output OUT8 15 14 O Constant current output OUT9 16 15 O Constant current output OUT10 17 16 O Constant current output OUT11 18 17 O Constant current output OUT12 19 18 O Constant current output OUT13 20 19 O Constant current output OUT14 21 20 O Constant current output OUT15 22 21 O Constant current output VCC 28 27 — Power-supply voltage VUP 26 25 — Pre-charge FET power supply GND 1 30 — Power ground 12, 13, NC — — No internal connection 28, 29 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5944 |
Аналогичный номер детали - TLC5944_1 |
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Аналогичное описание - TLC5944_1 |
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