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AD5422 датащи(PDF) 11 Page - Analog Devices

номер детали AD5422
подробное описание детали  Single Channel, 12/16-Bit, Serial Input, Current Source & Voltage Output DAC
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

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Preliminary Technical Data
AD5412/AD5422
Rev. PrF | Page 11 of 38
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AGND
SDO
AVSS
+VSENSE
FAULT
GND
LATCH
CLEAR
CLEAR SELECT
REFIN
SELECT
SCLK
SDIN
GND
RSET
VOUT
BOOST
CCOMP
REFOUT
TOP VIEW
(Not to Scale)
DVCC
NC
I OUT
-VSENSE
AVDD
DVCC
AD5412/
AD5422
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
LATCH
CLEAR SELECT
GND
FAULT
NC
NC
NC
DVCC SELECT
BOOST
CCOMP
NC
IOUT
NC
SDO
SDIN
SCLK
NC
CLEAR
TOP VIEW
(Not to Scale)
AD5412/
AD5422
CAP2
CAP1
Figure 5. TSSOP Pin Configuration
Figure 6. LFCSP Pin Configuration
Table 6. Pin Function Descriptions
TSSOP Pin No.
LFCSP Pin No.
Mnemonic
Description
1
14,37
AVSS
Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be
connected to 0V if output voltage range is unipolar.
2
39
DVCC
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
3
2
FAULT
Fault alert, This pin is asserted low when an open circuit is detected in current mode or
an over temperature is detected. Open drain output, must be connected to a pull-up
resistor.
4,12
3,15
GND
These pins must be connected to 0V.
18
1,10,11,19,
20,21,22,25,30,
31,35,38,40
NC
No Connection. Do not connect to this pin.
5
4
CLEAR
SELECT
Selects the voltage output clear value, either zero-scale or mid-scale code. See Table 21
6
5
CLEAR
Active High Input. Asserting this pin will set the current output to the bottom of the
selected range or will set the voltage output to the user selected value (zero-scale or
mid-scale).
7
6
LATCH
Positive edge sensitive latch, a rising edge will parallel load the input shift register data
into the DAC register, also updating the output.
8
7
SCLK
Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This
operates at clock speeds up to 30 MHz.
9
8
SDIN
Serial Data Input. Data must be valid on the rising edge of SCLK.
10
9
SDO
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback
mode. Data is valid on the rising edge of SCLK . See Figure 3 and Figure 4.
11
12
AGND
Ground reference pin for analog circuitry.
N/A
13
DGND
Ground reference pin for digital circuitry. (AGND and DGND are internally connected in
TSSOP package).
13
16
RSET
An external, precision, low drift 15k
Ω current setting resistor can be connected to this
pin to improve the IOUT temperature drift performance. Refer to Features section.
14
17
REFOUT
Internal Reference Voltage Output. REFOUT = 5 V ± 2 mV.
15
18
REFIN
External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for
specified performance.
16
23
DVCC
SELECT
This pin when connected to GND disables the internal supply and an external supply
must be connected to the DVCC pin. Leave this pin unconnected to enable the internal
supply. Refer to features section.
17
24
CCOMP
Optional compensation capacitor connection for the voltage output buffer. Connecting
a 4nF capacitor between this pin and the VOUT pin will allow the voltage output to drive
up to 1µF. It should be noted that the addition of this capacitor will reduce the


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