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74LVT574PW датащи(PDF) 8 Page - NXP Semiconductors |
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74LVT574PW датащи(HTML) 8 Page - NXP Semiconductors |
8 / 16 page 74LVT_LVTH574_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 September 2008 8 of 16 NXP Semiconductors 74LVT574; 74LVTH574 3.3 V octal D-type flip-flop; 3-state 11. Waveforms Measurement points are given in Table 8 VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delay clock input (CP) to output (Qn), pulse width clock (CP) and maximum clock frequency 001aac445 CP input Qn output tPHL tPLH tWH tWL 1/fmax VM VOH VI GND VOL VM Measurement points are given in Table 8 VOL and VOH are typical voltage output levels that occur with the output load. Measurement points are given in Table 8 VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Output enable time to HIGH-state and output disable time from HIGH-state Fig 8. Output enable time to LOW-state and output disable time from LOW-state Qn output 001aae468 OE input VM VI VOH GND GND tPZH tPHZ VY VM VM 001aae469 tPZL tPLZ VM VM VM Qn output OE input VI VOL 3.0 V VX GND Measurement points are given in Table 8 Remark: The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Data setup and hold times 001aac738 VM CP input VM VM VM VM VM tsu(H) th(H) tsu(L) th(L) Dn input Vl GND Vl GND |
Аналогичный номер детали - 74LVT574PW |
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Аналогичное описание - 74LVT574PW |
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