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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CDK1302AEMQ80_Q датащи(PDF) 8 Page - Cadeka Microcircuits LLC. |
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CDK1302AEMQ80_Q датащи(HTML) 8 Page - Cadeka Microcircuits LLC. |
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8 / 9 page  ©2008 CADEKA Microcircuits LLC www.cadeka.com 8 Data Sheet Operation The CDK1302 has 256 preamp/comparator pairs which are each supplied with the voltage from VRT to VRB divided equally by the resistive ladder as shown in the block diagram. This voltage is applied to the positive input of each preamplifier/comparator pair. An analog input volt- age applied at VIN is connected to the negative inputs of each preamplifier/comparator pair. The comparators are then clocked through each one’s individual clock buffer. When the CLK pin is in the low state, the master or input stage of the comparators compare the analog input volt- age to the respective reference voltage. When the CLK pin changes from low to high the comparators are latched to the state prior to the clock transition and output logic codes in sequence from the top comparators, closest to VRT (0V), down to the point where the magnitude of the input signal changes sign (thermometer code). The output of each comparator is then registered into four 64-to-6 bit decoders when the CLK is changed from high to low. At the output of the decoders is a set of four 7-bit latches which are enabled (“track”) when the clock changes from high to low. From here, the output of the latches are coded into 6 LSBs from 4 columns and 4 columns are coded into 2 MSBs. Finally, 8 ECL output latches and buffers are used to drive the external loads. The conversion takes one clock cycle from the input to the data outputs. Figure 2. Timing Diagram |
Аналогичный номер детали - CDK1302AEMQ80_Q |
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Аналогичное описание - CDK1302AEMQ80_Q |
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