SN74ALVCH162268

12-BIT TO 24-BIT REGISTERED BUS EXCHANGER

WITH 3-STATE OUTPUTS

SCES018G – AUGUST 1995 – REVISED JUNE 1999

7

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figures 1 through 3)

VCC = 1.8 V

VCC = 2.5 V

± 0.2 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

†

120

125

150

MHz

tw

Pulse duration, CLK high or low

†

3.3

3.3

3.3

ns

A data before CLK

↑

†

4.5

4

3.4

B data before CLK

↑

†

0.8

1.2

1

t

Setup time

SEL before CLK

↑

†

1.4

1.6

1.3

ns

tsu

Setup time

CLKENA1 or CLKENA2 before CLK

↑

†

3.6

3.4

2.8

ns

CLKENB1 or CLKENB2 before CLK

↑

†

3.2

3

2.5

OE before CLK

↑

†

4.2

3.9

3.2

A data after CLK

↑

†

0

0

0.2

B data after CLK

↑

†

1.3

1.2

1.3

th

Hold time

SEL after CLK

↑

†

1

1

1

ns

th

Hold time

CLKENA1 or CLKENA2 after CLK

↑

†

0.1

0.1

0.4

ns

CLKENB1 or CLKENB2 after CLK

↑

†

0.1

0

0.5

OE after CLK

↑ after CLK↑

†

0

0

0.2

† This information was not available at the time of publication.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figures 1 through 3)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 1.8 V

VCC = 2.5 V

± 0.2 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MIN

MAX

MIN

MAX

MIN

MAX

fmax

†

120

125

150

MHz

B

†

1.6

6.1

5.9

1.8

5.4

t d

CLK

A (1B)

†

1.6

5.8

5.4

1.7

4.8

ns

tpd

CLK

A (2B)

†

1.6

5.8

5.3

1.8

4.8

ns

A (SEL)

†

2.5

7.3

6.5

2.4

5.8

ten

CLK

B

†

2.7

7.2

6.8

2.6

6.1

ns

tdis

CLK

B

†

2.8

7.2

6.1

2.5

5.9

ns

ten

CLK

A

†

2

6.2

5.6

1.8

5.1

ns

tdis

CLK

A

†

2

6.5

5.4

2.1

5

ns

† This information was not available at the time of publication.

PARAMETER

TEST CONDITIONS

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V

UNIT

PARAMETER

TEST CONDITIONS

TYP

TYP

TYP

UNIT

C d

Power dissipation

Outputs enabled

CL =50 pF

f=10MHz

†

87

120

pF

Cpd

capacitance

Outputs disabled

CL = 50 pF,

f = 10 MHz

†

80.5

118

pF

† This information was not available at the time of publication.