SN74ALVCH16373

16-BIT TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

SCES020C – JULY 1995 – REVISED FEBRUARY 1999

1

POST OFFICE BOX 655303

Widebus

™ Family

CMOS) Submicron Process

MIL-STD-833, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

JESD 17

Need for External Pullup/Pulldown

Resistors

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

description

This 16-bit transparent D-type latch is designed

The SN74ALVCH16373 is particularly suitable for

implementing

buffer

registers,

I/O

ports,

bidirectional bus drivers, and working registers.

This device can be used as two 8-bit latches or

one 16-bit latch. When the latch-enable (LE) input

is high, the Q outputs follow the data (D) inputs.

When LE is taken low, the Q outputs are latched

at the levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus

lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old

data can be retained or new data can be entered while the outputs are in the high-impedance state.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16373 is characterized for operation from –40

°C to 85°C.

DGG OR DL PACKAGE

(TOP VIEW)

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1OE

1Q1

1Q2

GND

1Q3

1Q4

1Q5

1Q6

GND

1Q7

1Q8

2Q1

2Q2

GND

2Q3

2Q4

2Q5

2Q6

GND

2Q7

2Q8

2OE

1LE

1D1

1D2

GND

1D3

1D4

1D5

1D6

GND

1D7

1D8

2D1

2D2

GND

2D3

2D4

2D5

2D6

GND

2D7

2D8

2LE

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright

© 1999, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.