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TL16C550B датащи(PDF) 8 Page - Texas Instruments |
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TL16C550B датащи(HTML) 8 Page - Texas Instruments |
8 / 35 page TL16C550B, TL16C550BI ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS136B – JANUARY 1994 – REVISED AUGUST 1996 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 system timing requirements over recommended ranges of supply voltage and operating free-air temperature PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT tcR Cycle time, read (tw7 + td8 + td9) RC 87 ns tcW Cycle time, write (tw6 + td5 + td6) WC 87 ns tw1 Pulse duration, clock high tXH 1 f = 9 MHz maximum 40 ns tw2 Pulse duration, clock low tXL 1 f = 9 MHz maximum 40 ns tw5 Pulse duration, address strobe low tADS 2,3 9 ns tw6 Pulse duration, write strobe tWR 2 40 ns tw7 Pulse duration, read strobe tRD 3 40 ns tw8 Pulse duration, master reset tMR 1 µs tsu1 Setup time, address valid before ADS ↑ tAS 2,3 8 ns tsu2 Setup time, chip select valid before ADS ↑ tCS 2,3 8 ns tsu3 Setup time, data valid before WR1 ↓ or WR2↑ tDS 2 15 ns th1 Hold time, address low after ADS ↑ tAH 2,3 0 ns th2 Hold time, chip select valid after ADS ↑ tCH 2,3 0 ns th3 Hold time, chip select valid after WR1 ↑ or WR2↓ tWCS 2 10 ns th4 Hold time, address valid after WR1 ↑ or WR2↓ tWA 2 10 ns th5 Hold time, data valid after WR1 ↑ or WR2↓ tDH 2 5 ns th6 Hold time, chip select valid after RD1 ↑ or RD2↓ tRCS 3 10 ns th7 Hold time, address valid after RD1 ↑ or RD2↓ tRA 3 20 ns td4† Delay time, chip select valid before WR1 ↓ or WR2↑ tCSW 2 7 ns td5† Delay time, address valid before WR1 ↓ or WR2↑ tAW 2 7 ns td6† Delay time, write cycle, WR1 ↑ or WR2↓ to ADS↓ tWC 2 40 ns td7† Delay time, chip select valid to RD1 ↓ or RD2↑ tCSR 3 7 ns td8† Delay time, address valid to RD1 ↓ or RD2↑ tAR 3 7 ns td9 Delay time, read cycle, RD1 ↑ or RD2↓ to ADS↓ tRC 3 40 ns td10 Delay time, RD1 ↓ or RD2↑ to data valid tRVD 3 CL = 75 pF 45 ns td11 Delay time, RD1 ↑ or RD2↓ to floating data tHZ 3 CL = 75 pF 20 ns † Only applies when ADS is low system switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 2) PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT tdis(R) Disable time, RD1↑↓ or RD2↓↑ to DDIS↑↓ tRDD 3 CL = 75 pF 20 ns NOTE 2: Charge and discharge time is determined by VOL, VOH, and external loading. baud generator switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 75 pF PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT tw3 Pulse duration, BAUDOUT low tLW 1 f = 9 MHz, CLK ÷ 2 80 ns tw4 Pulse duration, BAUDOUT high tHW 1 f = 9 MHz, CLK ÷ 2 80 ns td1 Delay time, XIN ↑ to BAUDOUT↑ tBLD 1 75 ns td2 Delay time, XIN ↑↓ to BAUDOUT↓ tBHD 1 65 ns |
Аналогичный номер детали - TL16C550B |
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Аналогичное описание - TL16C550B |
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