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TL16C750Y датащи(PDF) 11 Page - Texas Instruments |
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TL16C750Y датащи(HTML) 11 Page - Texas Instruments |
11 / 35 page TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 commercial maximum switching characteristics, VCC = 4.75 V, TJ = 115°C PARAMETER FROM TO INTRINSIC DELAY DELTA DELAY DELAY (ns) PARAMETER (INPUT) (OUTPUT) DELAY (ns) DELAY (ns/pF) CL = 15 pF CL = 50 pF CL = 85 pF CL = 100 pF tPLH XIN XO – 0.92 0.571 7.65 27.66 47.66 56.23 tPHL XIN XO – 0.79 0.312 3.89 14.83 25.76 30.45 tr Output rise time, XO 10.86 40.42 69.98 82.65 tf Output fall time, XO 5.47 20.90 36.34 42.95 commercial maximum switching characteristics, VCC = 3 V, TJ = 115°C PARAMETER FROM TO INTRINSIC DELAY DELTA DELAY DELAY (ns) PARAMETER (INPUT) (OUTPUT) DELAY (ns) DELAY (ns/pF) CL = 15 pF CL = 50 pF CL = 85 pF CL = 100 pF tPLH XIN XO – 4.69 1.017 10.57 46.16 81.75 97.00 tPHL XIN XO – 3.05 0.442 3.58 19.04 34.51 41.13 tr Output rise time, XO 14.39 64.87 115.35 136.98 tf Output fall time, XO 5.06 26.53 48.01 57.21 receiver switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 10) PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT td12 Delay time, RCLK to sample clock tSCD 7 10 ns td13 Delay time, stop to set receiver error inter- rupt or read RBR to LSI interrupt or stop to RXRDY ↓ tSINT 7, 8, 9, 10, 11 2 RCLK cycle td14 Delay time, read RBR/LSR low to reset interrupt low tRINT 7, 8, 9, 10, 11 CL = 75 pF 120 ns NOTE 10: In the FIFO mode, the read cycle (RC) = 425 ns (minimum) between reads of the receive FIFO and the status registers (interrupt identification register or line status register). transmitter switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER† ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT td15 Delay time, INTRPT to transmit start tIRS 12 8 24 baudout cycles td16 Delay time, start to interrupt tSTI 12 8 10 baudout cycles td17 Delay time, WR THR to reset interrupt tHR 12 CL = 75 pF 50 ns td18 Delay time, initial write to interrupt (THRE) tSI 12 16 34 baudout cycles td19 Delay time, read IIR to reset interrupt (THRE) tIR 12 CL = 75 pF 70 ns td20 Delay time, write to TXRDY inactive tWXI 13, 14 CL = 75 pF 75 ns td21 Delay time, start to TXRDY active tSXA 13, 14 CL = 75 pF 9 baudout cycles † THRE = transmitter holding register empty, IIR = interrupt identification register. |
Аналогичный номер детали - TL16C750Y |
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Аналогичное описание - TL16C750Y |
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