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TSB41LV06A датащи(PDF) 9 Page - Texas Instruments

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номер детали TSB41LV06A
подробное описание детали  IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER
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TSB41LV06A
IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER
SLLS363 – SEPTEMBER1999
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
TYPE
I/O
DESCRIPTION
NAME
NO.
TYPE
I/O
DESCRIPTION
TPB0+
TPB1+
TPB2+
TPB3+
TPB4+
TPB5+
37
53
59
65
71
86
Cable
I/O
Twisted-pair cable B differential signal terminals. Board traces from each pair of positive and
negative differential signal terminals should be kept matched and as short as possible to the
TPB0–
TPB1–
TPB2–
TPB3–
TPB4–
TPB5–
36
52
58
64
70
85
Cable
I/O
negative differential signal terminals should be kept matched and as short as possible to the
external load resistors and to the cable connector.
TPBIAS0
TPBIAS1
TPBIAS2
TPBIAS3
TPBIAS4
TPBIAS5
40
56
62
68
74
89
Cable
I/O
Twisted-pair bias output. This provides the 1.86 V nominal bias voltage needed for proper operation
of the twisted–pair cable drivers and receivers, and for signaling to the remote nodes that there is an
active cable connection. Each of these terminals, except for an unused port, must be decoupled
with a 1-
µF capacitor to ground. For the unused port, this terminal can be left unconnected.
R0
R1
83
84
Bias
Current setting resistor terminals. These terminals are connected to an external resistance to set
the internal operating currents and cable driver output currents. A resistance of 6.30 k
Ω ±1% is
required to meet the IEEE Std 1394-1995 output voltage limits.
XI
XO
96
97
Crystal
Crystal oscillator inputs. These terminals connect to a 24.576 MHz parallel resonant fundamental
mode crystal. The optimum values for the external shunt capacitors are dependent on the
specifications of the crystal used
(see crystal selection in the applications information section).
VDD_5V
12
Supply
5-V VDD terminal. This terminal should be connected to the LLC VDD supply when a 5-V LLC is
used, and should be connected to the PHY DVDD when a 3-V LLC is used. A combination of high
frequency decoupling capacitors near this terminal is suggested, such as paralleled 0.1
µF and
0.001
µF. When this terminal is tied to a 5-V supply, all terminal bus holders are disabled, regardless
of the state of the ISO terminal. When this terminal is tied to a 3-V supply, bus holders are enabled
when the ISO terminal is high.
RESET
98
CMOS
I
Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to
VDD is provided so only an external delay capacitor in parallel with a resistor is required for proper
power-up operation (see
power-up reset in the applications information section). The RESET
terminal also incorporates an internal pull-down which is activated when the PD input is asserted
high. This input is otherwise a standard logic input, and may also be driven by an open-drain type
driver.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1)
–0.3 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1)
–0.5 V to VCC + 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5V tolerant I/O supply voltage range, VDD_5V
–0.3 V to 5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5V tolerant input voltage range, VI_5V
–0.5 V to VDD_5V + 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range at any output, VO
–0.5 V to VDD + 0.5V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (see Note 2)
HBM: 2 kV, MM: 200 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation
See Dissipation Rating Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free air temperature,TA
0
_C to 70_C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
–65
_C to 150_C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
_C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. All voltage values, except differential I/O bus voltages, are with respect to network ground.
2. HBM is Human Body Model, MM is Machine Model.


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