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UC1849 датащи(PDF) 7 Page - Texas Instruments

номер детали UC1849
подробное описание детали  Secondary Side Average Current Mode Controller
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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UC1849 датащи(HTML) 7 Page - Texas Instruments

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current discharge and subsequent charge cycles whether
or not other units on the CLKSYN bus are still synchro-
nizing. This requires the frequency of all free running
oscillators to be within 40% of each other to guarantee
synchronization.
Grounds, Voltage Sensing and Current Sensing: The
voltage is sensed directly at the load. Proper load sharing
requires the same sensed voltage for each power supply
connected in parallel. Referring to Figure 6, the positive
sense voltage (VSP) connects to the voltage error ampli-
fier inverting terminal (VA-), the return lead for the on-
chip reference is used as the negative sense (VSM). The
current is sensed across the shunt resistor, RS.
Figure 6 shows one recommended voltage and current
sensing scheme when VEE is connected to GND. The
signal ground is the negative sense point for the output
voltage and the positive sense point for the output cur-
rent. The voltage offset on the current sense amplifier is
not needed if VEE is separated from GND. VEE is the
negative supply for the current sense amplifier. When it is
separated from GND, it extends the current sense ampli-
fier’s common mode input voltage range to include VEE
which is approximately
−0.7V below ground. The resistor
RADJ is used for load sharing. The unit which is the mas-
ter will force VADJ to 1.0V. Therefore, the regulated volt-
age being sensed is actually
RADJ
R1
+ RADJ
VSM = 0V, VADJ = 1V (master), VREF = 5V
RADJ
R1
+ RADJ
Figure 3. Output Frequency
Figure 4. Maximum Duty Cycle
Figure 5. Oscillator Synchronization
Connection Diagram
UDG-94113
Figure 6. Voltage and Current Sense VEE Tied to GND
UDG-94114
VSP
− VSM = (VREF − VADJ)
· () + VADJ
VSP = 4
· () + 1V
UC1849
UC2849
UC3849
CIRCUIT BLOCK DESCRIPTION (cont.)


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