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UC1860 датащи(PDF) 7 Page - Texas Instruments |
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UC1860 датащи(HTML) 7 Page - Texas Instruments |
7 / 9 page UC1860 UC2860 UC3860 OPEN LOOP LABORATORY TEST FIXTURE The open loop laboratory test fixture is designed to allow familiarization with the operating characteristics of the UC3860. Note the pin numbers apply to the DlP. To get started, preset all the options as follows: Adjust the error amplifier variable resistor pot (R1) so the wiper is at a high potential. Open the lVFO resistor switch (S1). Throw the Trig switch (S2) to ground. Throw the Osc Dsbl switch (S3) to ground. Throw the uncommitted comparator switch (S4) to ground. Throw the UVLO switch (S5) to the resistive divider. Throw the Out Mode switch (S6) to ground. Open the restart delay switch (S7). Throw the fault switch (S8)to ground. In this configuration, the chip will operate for Vcc greater than 12V. Adjustment of the following controls allows ex- amination of specific features. R1 adjusts the output of the error amp. Notice the voltage at pin 5 is limited from 0 to 2V above the voltage at pin 7. S1 changes the error amp output to VFO gain. With S1 open, the maximum frequency is determined by the error amp output. With S1 closed, the one shot will set the maximum frequency. S2 demonstrates the trigger. An external trigger signal may be applied. When the switch is set to the resistive di- vider, the chip will operate in consecutive mode (ie: A,B, off,...) S3 allows input of an external logic signal to disable the oscillator. S4 demonstrates the uncommitted comparator. When set to output A, the comparator will accelerate the discharge of pin 9, shortening the output pulse. S5 shorted to ground will disable the chip and the outputs will be low. If the switch is open, the VCC start and stop thresholds are 17 and 10V. Switched to the resistive di- vider, the thresholds are approximately 12 and 10V. S6 sets the mode of the toggle flip-flop. When grounded, the outputs operate alternately. Switched to 5V, the out- puts switch in unison. (Note: If S6 and S2 are set for uni- son operation and triggered consecutive outputs, the chip will free run at the maximum frequency determined by the one shot.) S7 open allows the chip to restart immediately after a fault sense has been removed. When grounded, it causes the chip to latch off indefinitely. This state can be reset by UVLO, VCC, or opening the switch. Connected to I µF pro- grams a hic-up delay time of 600 ms. S8 allows the simulation of a fault state. When flipped to the RC network, the comparator monitors scaled average voltage of output B. Adjusting frequency will cause the comparator to sense a ’fault’ and the chip will enter fault sequence. 7 |
Аналогичный номер детали - UC1860 |
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Аналогичное описание - UC1860 |
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