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UC2914 датащи(PDF) 6 Page - Texas Instruments |
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UC2914 датащи(HTML) 6 Page - Texas Instruments |
6 / 14 page 6 UC1914 UC2914 UC3914 Figure 2. Fault timing circuitry for the UC3914, including power limit and overcurrent. UDG-97052 The UC3914 is to be used in conjunction with external passive components and an N-channel MOSFET (NMOS) to facilitate hot swap capability of application modules. A typical application set-up is given in Fig. 9. The term hot swap refers to the system requirement that submodules be swapped in or out upon failure or system modification without removing power to the operating hardware. The integrity of the power bus must not be compromised due to the addition of an unpowered mod- ule. Significant power bus glitches can occur due to the substantial initial charging current of on-board module bypass capacitance and other load conditions (for more information on hot swapping and power management ap- plications, see Application Note U-151). The UC3914 provides protection by monitoring and controlling the out- put current of an external NMOS to charge this capaci- tance and provide load current. The addition of the NMOS, a sense resistor, RSENSE, and two other resis- tors, R1 and R2, sets the programmed maximum current level the NMOS can source to charge the load in a con- trolled manner. The equation for this current, IMAX, is: I VV R MAX CC IMAX SENSE = − where VIMAX is the voltage generated at the IMAX pin. Analysis of the application circuit shows that VIMAX (with respect to GND) can be defined as: () VV VV R RR VR RR V IMAX REF CC REF REF =+ −• + = • + + 1 12 21 12 where VREF is the voltage on the REF pin and whose in- ternally generated potential is two volts below VCC. The UC3914 also has an internal overcurrent comparator which monitors the voltage between SENSE and VCC. If this voltage exceeds 50mV, the comparator determines that a fault has occurred, and a timing capacitor, CT, will begin to charge. This can be rewritten as a current which causes a fault, IFAULT: I mV R FAULT SENSE = 50 Fault Timing Fig. 2 shows the circuitry associated with the fault timing function of the UC3914. A typical fault mode, where the overload comparator and current source I3 do not factor into operation (switch S2 is open), will first be consid- ered. Once the voltage across RSENSE exceeds 50mV, a fault has occurred. This causes the timing capacitor, CT, to charge with a combination of 100 µA (I1) plus the cur- rent from the power limiting circuitry (IPL). APPLICATION INFORMATION |
Аналогичный номер детали - UC2914 |
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Аналогичное описание - UC2914 |
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