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UC2914 датащи(PDF) 7 Page - Texas Instruments

номер детали UC2914
подробное описание детали  5V to 35V Hot Swap Power Manager
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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UC2914 датащи(HTML) 7 Page - Texas Instruments

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UC1914
UC2914
UC3914
Figure 3a: Typical timing diagram.
UDG-97054
t0: Normal conditions - output current is nominal, output
voltage is at positive rail, VCC
t1: Fault control reached - output current rises above the
programmed fault value, CT begins to charge with ≅
100
µA + IPL.
t2: Maximum current reached - output current reaches
the programmed maximum level and becomes a con-
stant current with value IMAX.
t3: Fault occurs - CT has charged to 2.5V, fault output
goes low, the FET turns off allowing no output current
to flow, VOUT discharge to GND.
t4: Retry - CT has discharged to 0.5V, but fault current
is still exceeded, CT begins charging again, FET is on,
VOUT increases.
t5 = t3: Illustrates <3% duty cycle depending upon
RPL selected.
t6 = t4
t7 = t0: Fault released, normal condition - return to
normal operation of the hot swap power manager.
Fig. 3a shows typical fault timing waveforms for the ex-
ternal NMOS output current, the voltage on the CT pin,
and the output load voltage, VOUT, with LR left floating or
grounded. The output voltage waveforms have assumed
an RC characteristic load and time constants will vary de-
pending upon the component values. Prior to time t0, the
load is fully charged to almost VCC and the NMOS is
supplying the current, IO, to the load. At t0, the current
begins to ramp up due to a change in the load conditions
until, at t1, the fault current level, IFAULT, has been
reached to cause switch S1 to close. This results in CT
being charged with the current sources I1 and IPL. Dur-
ing this time, VOUT is still almost equal to VCC except for
small losses from voltage drops across the sense resis-
tor and the NMOS. The output current reaches the pro-
grammed maximum level, IMAX, at t2. The CT voltage
continues to rise since IMAX is still greater than IFAULT.
The load output voltage drops because the current load
requirements have become greater than the controlled
maximum sourcing current. The CT voltage reaches the
upper comparator threshold (Fig. 2) of 2.5V at t3, which
promptly shuts off the gate drive to the NMOS (not
APPLICATION INFORMATION (cont.)


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