поискавой системы для электроныых деталей |
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UC2914 датащи(PDF) 9 Page - Texas Instruments |
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UC2914 датащи(HTML) 9 Page - Texas Instruments |
9 / 14 page 9 UC1914 UC2914 UC3914 Figure 3b. Typical timing diagram utilizing LR (Latch Reset) function. APPLICATION INFORMATION (cont.) t0: Normal conditions - output current is nominal, output voltage is at positive rail, VCC t1: Fault control reached - output current rises above the programmed fault value, CT begins to charge with ≅ 100 µA + IPL. t2: Maximum current reached - output current reaches the programmed maximum level and becomes a con- stant current with value IMAX. t3: Fault occurs - CT has charged to 2.5V, fault output goes low, the FET turns off allowing no output current to flow, VOUT discharge to GND. t4: Reset comparator threshold reached but no retry since LR pin held high. t5: LR toggled low, NMOS turned on and sources cur- rent to load. t6 = t3 t7: LR toggled low before VCT reaches reset compara- tor threshold, causing retry. t8: Since LR toggled low during present cycle, NMOS turned on and sources current to load. t9 = t0: Fault released, normal condition - return to normal operation of the hot swap power manager. UDG-97055 |
Аналогичный номер детали - UC2914 |
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Аналогичное описание - UC2914 |
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