поискавой системы для электроныых деталей |
|
CDK2000-CLK датащи(PDF) 11 Page - Cirrus Logic |
|
CDK2000-CLK датащи(HTML) 11 Page - Cirrus Logic |
11 / 30 page CS2000-OTP DS758F1 11 5. APPLICATIONS 5.1 One Time Programmability The one time programmable (OTP) circuitry in the CS2000-OTP allows for pre-configuration of the device prior to use in a system. There are two types of parameters that are used for device pre-configuration: modal and global. The modal parameters are features which, when grouped together, create a modal configuration set (see Figure 17 on page 22). Up to four modal configuration sets can be permanently stored and then dynamically selected using the M[1:0] mode select pins (see Table 1). The global parameters are the re- maining configuration settings which do not change with the mode select pins. The modal and global pa- rameters can be pre-set at the factory or user programmed using the customer development kit, CDK2000; Please see “Programming Information” on page 27 for more details. Table 1. Modal and Global Configuration 5.2 Timing Reference Clock Input The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an external crystal in conjunction with the internal oscillator. In order to maintain a stable and low-jitter PLL out- put the timing reference clock must also be stable and low-jitter; the quality of the timing reference clock directly affects the performance of the PLL and hence the quality of the PLL output. 5.2.1 Internal Timing Reference Clock Divider The Internal Timing Reference Clock (SysClk) is limited to a lower maximum frequency than that allowed on the XTI/REF_CLK pin. The CS2000-OTP supports the wider external frequency range by offering an internal divider for RefClk. The RefClkDiv[1:0] global parameter should be configured such that SysClk, the divided RefClk, then falls within the valid range as indicated in “AC Electrical Characteristics” on page 7. It should be noted that the maximum allowable input frequency of the XTI/REF_CLK pin is dependent upon its configuration as either a crystal connection or external clock input. See the “AC Electrical Char- acteristics” on page 7 for more details. For the lowest possible output jitter, attention should be paid to the absolute frequency of the Timing Ref- erence Clock relative to the PLL Output frequency (CLK_OUT). To minimize output jitter, the Timing Ref- erence Clock frequency should be chosen such that fRefClk is at least +/-15 kHz from fCLK_OUT*N/32 where N is an integer. Figure 9 shows the effect of varying the RefClk frequency around fCLK_OUT*N/32. It should be noted that there will be a jitter null at the zero point when N = 32 (not shown in Figure 9). An Parameter Type M[1:0] pins = 00 M[1:0] pins = 01 M[1:0] pins = 10 M[1:0] pins = 11 Modal Configuration Set 0 Ratio 0 Configuration Set 1 Ratio 1 Configuration Set 2 Ratio 2 Configuration Set 3 Ratio 3 Global Configuration settings set once for all modes. Figure 8. Internal Timing Reference Clock Divider N Internal Timing Reference Clock PLL Output Fractional-N Frequency Synthesizer Timing Reference Clock Divider ÷1 ÷2 ÷4 XTI/REF_CLK RefClkDiv[1:0] 8 MHz < SysClk < 14 MHz 8 MHz < RefClk < Timing Reference Clock 50 MHz (XTI) 58 MHz (REF_CLK) |
Аналогичный номер детали - CDK2000-CLK |
|
Аналогичное описание - CDK2000-CLK |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |