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CS2100CP-CZZR датащи(PDF) 2 Page - Cirrus Logic |
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CS2100CP-CZZR датащи(HTML) 2 Page - Cirrus Logic |
2 / 32 page CS2100-CP 2 DS840F1 TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 4 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 PLL PERFORMANCE PLOTS ............................................................................................................... 8 CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT ................................................... 9 CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ............................................... 10 4. ARCHITECTURE OVERVIEW ............................................................................................................. 11 4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 11 4.2 Hybrid Analog-Digital Phase Locked Loop ....................................................................................11 5. APPLICATIONS ................................................................................................................................... 13 5.1 Timing Reference Clock Input ........................................................................................................ 13 5.1.1 Internal Timing Reference Clock Divider ............................................................................... 13 5.1.2 Crystal Connections (XTI and XTO) ...................................................................................... 14 5.1.3 External Reference Clock (REF_CLK) .................................................................................. 14 5.2 Frequency Reference Clock Input, CLK_IN ................................................................................... 14 5.2.1 CLK_IN Skipping Mode ......................................................................................................... 14 5.2.2 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 16 5.3 Output to Input Frequency Ratio Configuration ............................................................................. 17 5.3.1 User Defined Ratio (RUD) ..................................................................................................... 17 5.3.2 Ratio Modifier (R-Mod) .......................................................................................................... 18 5.3.3 Effective Ratio (REFF) .......................................................................................................... 19 5.3.4 Ratio Configuration Summary ............................................................................................... 19 5.4 PLL Clock Output ........................................................................................................................... 20 5.5 Auxiliary Output .............................................................................................................................. 20 5.6 Clock Output Stability Considerations ............................................................................................ 21 5.6.1 Output Switching ................................................................................................................... 21 5.6.2 PLL Unlock Conditions .......................................................................................................... 21 5.7 Required Power Up Sequencing .................................................................................................... 21 6. SPI / I²C CONTROL PORT ................................................................................................................... 21 6.1 SPI Control ..................................................................................................................................... 22 6.2 I²C Control ...................................................................................................................................... 22 6.3 Memory Address Pointer ............................................................................................................... 24 6.3.1 Map Auto Increment .............................................................................................................. 24 7. REGISTER QUICK REFERENCE ........................................................................................................ 24 8. REGISTER DESCRIPTIONS ................................................................................................................ 25 8.1 Device I.D. and Revision (Address 01h) ....................................................................................... 25 8.1.1 Device Identification (Device[4:0]) - Read Only ..................................................................... 25 8.1.2 Device Revision (Revision[2:0]) - Read Only ........................................................................ 25 8.2 Device Control (Address 02h) ........................................................................................................ 25 8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 25 8.2.2 Auxiliary Output Disable (AuxOutDis) ................................................................................... 25 8.2.3 PLL Clock Output Disable (ClkOutDis) .................................................................................. 26 8.3 Device Configuration 1 (Address 03h) ........................................................................................... 26 8.3.1 R-Mod Selection (RModSel[2:0]) ...........................................................................................26 8.3.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 26 8.3.3 Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................ 27 8.4 Global Configuration (Address 05h) ............................................................................................... 27 8.4.1 Device Configuration Freeze (Freeze) ................................................................................ 27 |
Аналогичный номер детали - CS2100CP-CZZR |
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Аналогичное описание - CS2100CP-CZZR |
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