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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9551BCPZ-REEL7 датащи(PDF) 3 Page - Analog Devices |
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AD9551BCPZ-REEL7 датащи(HTML) 3 Page - Analog Devices |
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3 / 40 page  AD9551 Rev. B | Page 3 of 40 The AD9551 is easily configured using the external control pins (A[3:0], B[3:0], and Y[3:0]). The logic state of these pins sets pre- defined divider values that establish a specific input-to-output frequency ratio. For applications requiring other frequency ratios, the user can override any of the preconfigured divider settings via the serial port, which enables a very wide range of applications. The AD9551 architecture consists of two cascaded PLL stages. The first stage consists of fractional division (via SDM), followed by a digital PLL that uses a crystal resonator-based DCXO. The DCXO relies on an external crystal with a resonant frequency in the range of 19.44 MHz to 52 MHz. The DCXO constitutes the first PLL, which operates within a narrow frequency range (±50 ppm) around the crystal resonant frequency. This PLL has a loop bandwidth of approximately 180 Hz, providing initial jitter cleanup of the input reference signal. The second stage is a fre- quency multiplying PLL that translates the first stage output frequency (in the range of 19.44 MHz to 104 MHz) up to ~3.7 GHz. This PLL incorporates an SDM-based fractional feedback divider that enables fractional frequency multiplication. Programmable integer dividers at the output of this second PLL establish a final output frequency of up to 900 MHz. It is important to understand that the architecture of the AD9551 produces an output frequency that is most likely not coherent with the input reference frequency. The reason is that the input and crystal frequencies typically are not harmonically related and neither are the output and crystal frequencies. As a result, there is generally no relationship between the phase of the input and output signals. The AD9551 includes reference signal processing blocks that enable a smooth switching transition between two reference inputs. This circuitry automatically detects the presence of the reference input signals. If only one input is present, the device uses it as the active reference. If both inputs are present, one becomes the active reference and the other becomes the alter- nate reference. The circuitry edge-aligns the backup reference with the active reference. If the active reference fails, the circuitry automatically switches to the backup reference (if available), making it the new active reference. Meanwhile, if the failed reference is once again available, it becomes the new backup reference and is edge-aligned with the new active reference (a precaution against failure of the new active reference). If neither reference can be used, the AD9551 supports a holdover mode. Note that the external crystal is necessary to provide the switchover and holdover functionality. It is also the clock source for the reference synchronization and monitoring functions. The AD9551 relies on a single external capacitor for the output PLL loop filter. With proper termination, the output is compatible with LVPECL, LVDS, or CMOS logic levels, although the AD9551 is implemented in a strictly CMOS process. The AD9551 operates over the extended industrial temperature range of −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM 19.44MHz MODE P F D VCO P0 P1 N1 4/5 CHARGE PUMP SDM N = 4N1 + N0 NA, MODA, FRACA NB, MODB, FRACB N, MOD, FRAC, P0, P1, P2 P2, P1, P0 N TEST MUX fIF fOUT1 LOCK DETECT LOOP CONFIGURATION DCXO DIG. LOOP FILTER P F D REFERENCE MONITOR SAMPLE RATE CONTROL 19.44MHz MODE 3 2 2 2 fOUT2 2 4 4 4 REGISTER BANK PRECONFIGURED DIVIDER VALUES NA SDMA NB SDMB fREFA fREFB 4 TO 11 1 TO 63 OUT1, OUT1 OUTPUT PLL LOCKED INPUT PLL LOCKED XTAL1 XTAL0 LF REFA, REFA REFB, REFB A[3:0] B[3:0] Y[3:0] SCLK, SDIO, CS OUT2, OUT2 1 TO 63 AD9551 3350MHz TO 4050MHz P2 Figure 2. |
Аналогичный номер детали - AD9551BCPZ-REEL7 |
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Аналогичное описание - AD9551BCPZ-REEL7 |
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