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FAN6861TY датащи(PDF) 3 Page - Fairchild Semiconductor |
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FAN6861TY датащи(HTML) 3 Page - Fairchild Semiconductor |
3 / 15 page © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6861 • Rev. 1.0.1 3 Marking Information Figure 3. Top Mark Pin Configuration Figure 4. Pin Configuration Pin Definitions Pin # Name Description 1 GND Ground. 2 FB This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin is higher than 4.6V for longer than 780ms, the overload protection is triggered and PWM output is disabled. 3 RT This pin is for programmable over-temperature protection. An external NTC thermistor is connected between this pin and GND pin. Once the voltage of this pin drops below a threshold of 0.7V, PWM output is disabled. 4 SENSE This pin is for current sense. This pin senses the voltage across a resistor. The voltage of this pin is compared with the feedback information determining the PWM duty cycle. 5 VDD This pin is the positive supply voltage input. 6 GATE The totem-pole output driver to drive the gate of power MOSFET. Soft driving waveform is implemented to reduce EMI. AAR: FAN6861 TT: Wafer lot code • • •: Year code _ _ _: Week code |
Аналогичный номер детали - FAN6861TY |
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Аналогичное описание - FAN6861TY |
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