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FIN210ACGFX датащи(PDF) 2 Page - Fairchild Semiconductor |
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FIN210ACGFX датащи(HTML) 2 Page - Fairchild Semiconductor |
2 / 17 page © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN210AC • Rev. 1.0.1 2 FIN210AC (Serializer DIRI=1) Pin Descriptions Pin Name Description 0 Deserializer DIRI Control to determine serializer or deserializer configuration. 1 Serializer 0 Low drive (low power) CTL_ADJ Adjusts CTL drive to compensate for environmental conditions and length. 1 High drive (high power) S0 Configure frequency range for the PLL. See Table 1 Serializer (DIRI=1) Control Pin. S1 Configure frequency range for the PLL. See Table 1 Serializer (DIRI=1) Control Pin. PLL0 Divide or adjust the serial frequency. See Table 1 Serializer (DIRI=1) Control Pin. PLL1 Divide or adjust the serial frequency. See Table 1 Serializer (DIRI=1) Control Pin. CKREF LV-CMOS clock input and PLL reference. STROBE LV-CMOS strobe input for latching data (DP [1:12]) into the serializer on the rising edge. DP[1:10] LV-CMOS parallel data input. (GND input if not used) CKSO+ CKSO- CTL Differential serializer output bit clock. CKSO+: Positive signal; CKSO-: Negative signal. DSO+ DSO- CTL Differential serial output data signals. DSO+: Positive signal; DSO-: Negative signal. CKSI+ CKSI- CTL Differential deserializer input bit clock. CKSI+: Positive signal; CKSI-: Negative signal. No connect unless in “clock pass-through” mode. CKP LV-CMOS word clock output or Pixel clock output. No connect unless in “clock pass-through” mode. /DIRO LV-CMOS output, Inversion of DIRI in normal operation. Can be used to drive the DIRI signal of the deserializer where the interface needs to be turned around. No connect if not used. VDDP Power supply for parallel I/O. (All VDDP pins must be connected to VDDP) VDDS Power supply for serial I/O. VDDA Power supply for core. GND All GND pins must be connected to ground. BGA: all GND pads. MLP: Pin 29 & GND PAD must be grounded. N/C No connect. (Do not connect to GND or VDD) Note: 1. 0=GND; 1=VDDP FIN210AC (Serializer DIRI=1) Pin Configurations GND DP[2] CKREF DP[5] DP[1] STROBE DP[3] VDDP GND PLL1 1 A 3456 2 B C D E F G DP[4] CTL_ADJ DP[6] /DIRO CKP CKSO+ CKSO- DP[7] DSO- DSO+ DP[8] DP[9] VDDS CKSI+ CKSI- DP[10] VDDA DIRI PLL0 S1 S0 GND GND GND N/C N/C N/C N/C N/C N/C N/C N/C SERIALIZER GND PAD DP[4] CKSO+ CKSO- DSO+ DSO- CKSI- CKSI+ DIRI VDDS 1 DP[5] 2 4 DP[6] VDDP 3 CKP 5 DP[7] 6 DP[8] 7 DP[9] 8 20 21 19 23 18 17 22 24 42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View) 32-pin MLP, 5 x 5mm, .5mm pitch (Top View) (Center pad must be grounded) Figure 2. FIN210AC (Serializer DIRI=1) Pin Assignments (Top View) |
Аналогичный номер детали - FIN210ACGFX |
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Аналогичное описание - FIN210ACGFX |
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