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TCA9535PWR датащи(PDF) 10 Page - Texas Instruments |
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TCA9535PWR датащи(HTML) 10 Page - Texas Instruments |
10 / 32 page Power-On Reset Interrupt (INT) Output Bus Transactions Writes 1 2 SCL 3 4 5 6 7 8 SDA A A A Data 0 9 0 0 0 0 0 0 0 1 0.7 0.0 Data 1 1.7 1.0 A S 0 1 0 0 A2 A1 A0 0 P Slave Address Command Byte Data to Port 0 Data to Port 1 Start Condition Acknowledge From Slave Write to Port Data Out from Port 1 Data Out from Port 0 Data Valid Acknowledge From Slave Acknowledge From Slave tpv tpv R/W TCA9535 SCPS201A – AUGUST 2009 – REVISED SEPTEMBER 2009........................................................................................................................................... www.ti.com When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9535 in a reset condition until VCC has reached VPOR. At that point, the reset condition is released, and the TCA9535 registers and I 2C/SMBus state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to the operating voltage for a power-reset cycle. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) bit or not acknowledge (NACK) bit after the falling edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa. INT has an open-drain structure and requires a pullup resistor to VCC. Data is exchanged between the master and the TCA9535 through write and read commands. Data is transmitted to the TCA9535 by sending the device address and setting the least-significant bit to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. The eight registers within the TCA9535 are configured to operate as four register pairs. The four pairs are Input Ports, Output Ports, Polarity Inversions, and Configurations. After sending data to one register, the next data byte is sent to the other register in the pair (see Figure 6 and Figure 7). For example, if the first byte is sent to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers. Figure 6. Write to Output Port Registers <br/> 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9535 |
Аналогичный номер детали - TCA9535PWR |
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Аналогичное описание - TCA9535PWR |
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