поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

FM24VN10-GTR датащи(PDF) 5 Page - Ramtron International Corporation

номер детали FM24VN10-GTR
подробное описание детали  1Mb Serial 3V F-RAM Memory
Download  15 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  RAMTRON [Ramtron International Corporation]
домашняя страница  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM24VN10-GTR датащи(HTML) 5 Page - Ramtron International Corporation

  FM24VN10-GTR Datasheet HTML 1Page - Ramtron International Corporation FM24VN10-GTR Datasheet HTML 2Page - Ramtron International Corporation FM24VN10-GTR Datasheet HTML 3Page - Ramtron International Corporation FM24VN10-GTR Datasheet HTML 4Page - Ramtron International Corporation FM24VN10-GTR Datasheet HTML 5Page - Ramtron International Corporation FM24VN10-GTR Datasheet HTML 6Page - Ramtron International Corporation FM24VN10-GTR Datasheet HTML 7Page - Ramtron International Corporation FM24VN10-GTR Datasheet HTML 8Page - Ramtron International Corporation FM24VN10-GTR Datasheet HTML 9Page - Ramtron International Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 15 page
background image
FM24V10 - 1Mb I2C FRAM
Rev. 1.1
Feb. 2009
Page 5 of 15
Figure 4. Slave Address
Addressing Overview
After the FM24V10 (as receiver) acknowledges the
slave address, the master can place the memory
address on the bus for a write operation. The address
requires a 1-bit page select and two bytes. Since the
device uses 17 address bits, the page select bit is the
MSB of the address followed by the remaining 16
address bits. The complete 17-bit address is latched
internally. Each access causes the latched address
value to be incremented automatically. The current
address is the value that is held in the latch -- either a
newly written value or the address following the last
access. The current address will be held for as long as
power remains or until a new value is written. Reads
always use the current address. A random read
address can be loaded by beginning a write operation
as explained below.
After transmission of each data byte, just prior to the
acknowledge, the FM24V10 increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing. After the
last address (1FFFFh) is reached, the address latch
will roll over to 0000h. There is no limit to the
number of bytes that can be accessed with a single
read or write operation.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM24V10 can begin. For a read operation the
FM24V10 will place 8 data bits on the bus then wait
for an acknowledge from the master. If the
acknowledge occurs, the FM24V10 will transfer the
next sequential byte. If the acknowledge is not sent,
the FM24V10 will end the read operation. For a write
operation, the FM24V10 will accept 8 data bits from
the master then send an acknowledge. All data
transfer occurs MSB (most significant bit) first.
Memory Operation
The FM24V10 is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of F-RAM
technology. These improvements result in some
differences between the FM24V10 and a similar
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.
Write Operation
All writes begin with a slave address, then a memory
address. The bus master indicates a write operation
by setting the LSB of the slave address (R/W bit) to a
‘0’. After addressing, the bus master sends each byte
of data to the memory and the memory generates an
acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range
is reached internally, the address counter will wrap
from 1FFFFh to 0000h.
Unlike other nonvolatile memory technologies, there
is no effective write delay with F-RAM. Since the
read and write access times of the underlying
memory are the same, the user experiences no delay
through the bus. The entire memory cycle occurs in
less time than a single bus clock. Therefore, any
operation including read or write can occur
immediately following a write. Acknowledge polling,
a technique used with EEPROMs to determine if a
write is complete is unnecessary and will always
return a ready condition.
Internally, an actual memory write occurs after the 8th
data bit is transferred. It will be complete before the
acknowledge is sent. Therefore, if the user desires to
abort a write without altering the memory contents,
this should be done using start or stop condition prior
to the 8th data bit. The FM24V10 uses no page
buffering.
The memory array can be write-protected using the
WP pin. This feature is available only on FM24V10
and FM24VN10 devices. Setting the WP pin to a
high condition (VDD) will write-protect all addresses.
The FM24V10 will not acknowledge data bytes that
are written to protected addresses. In addition, the
address counter will not increment if writes are
attempted to these addresses. Setting WP to a low
state (VSS) will deactivate this feature. WP is pulled
down internally.
Figures 5 and 6 below illustrate a single-byte and
multiple-byte write cycles.
1
01
0A2
R/W
Slave ID
76
5
4
3
2
1
0
A1
A16
Device
Select
Page
Select


Аналогичный номер детали - FM24VN10-GTR

производительномер деталидатащиподробное описание детали
logo
Ramtron International C...
FM24VN10-GTR RAMTRON-FM24VN10-GTR Datasheet
347Kb / 16P
   1Mb Serial 3V F-RAM Memory
logo
Cypress Semiconductor
FM24VN10-GTR CYPRESS-FM24VN10-GTR Datasheet
441Kb / 16P
   1Mb Serial 3V F-RAM Memory
FM24VN10-GTR CYPRESS-FM24VN10-GTR Datasheet
417Kb / 17P
   1Mb Serial 3V F-RAM Memory
More results

Аналогичное описание - FM24VN10-GTR

производительномер деталидатащиподробное описание детали
logo
Cypress Semiconductor
FM24V10 CYPRESS-FM24V10 Datasheet
441Kb / 16P
   1Mb Serial 3V F-RAM Memory
FM25V10 CYPRESS-FM25V10_13 Datasheet
484Kb / 17P
   1Mb Serial 3V F-RAM Memory
logo
Ramtron International C...
FM24V10 RAMTRON-FM24V10_10 Datasheet
347Kb / 16P
   1Mb Serial 3V F-RAM Memory
logo
Cypress Semiconductor
FM24V10 CYPRESS-FM24V10_13 Datasheet
417Kb / 17P
   1Mb Serial 3V F-RAM Memory
logo
Ramtron International C...
FM25V10 RAMTRON-FM25V10 Datasheet
333Kb / 16P
   1Mb Serial 3V F-RAM Memory
logo
Cypress Semiconductor
FM25V10 CYPRESS-FM25V10 Datasheet
531Kb / 16P
   1Mb Serial 3V F-RAM Memory
logo
Ramtron International C...
FM25V02 RAMTRON-FM25V02 Datasheet
343Kb / 17P
   256Kb Serial 3V F-RAM Memory
logo
Cypress Semiconductor
FM24CL64B CYPRESS-FM24CL64B Datasheet
354Kb / 13P
   64Kb Serial 3V F-RAM Memory
FM24V01 CYPRESS-FM24V01 Datasheet
378Kb / 14P
   128Kb Serial 3V F-RAM Memory
FM24V02 CYPRESS-FM24V02 Datasheet
401Kb / 16P
   256Kb Serial 3V F-RAM Memory
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15


датащи скачать

Go To PDF Page


ссылки URL




Конфиденциальность
ALLDATASHEETRU.COM
Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com