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BU7893GU датащи(PDF) 9 Page - Rohm |
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BU7893GU датащи(HTML) 9 Page - Rohm |
9 / 25 page 9/24 ● DIGITAL INTERFACE OF 16BIT AUDIO D/A CONVERTER 16bit audio D/A converter equipped with this series can be used with the following audio format. 【 BU7858KN】 1) MSB first 16bit data (Right justified) 2) MSB first 18bit data (Right justified) 3) IIS mode 18bit data (Left justified) 4) IIS mode 16bit data (BCLK=32fs) Fig.28 AUDIO I/F FORMAT (BU7858KN) BU7858KN is provided with a mode that generates MCLK (Master Clock) by using the built-in PLL, so it is possible to make a D/A converter operate even if the clocks are only BCLK (64fs/32fs), LRCLK (fs). The PLL generates MCLK (Master Clock), which is necessary for driving of D/A converter, from BCLK (Bit Clock). Please connect a capacitor (PLLC) for the filter with DVSS. Moreover, please place the capacitor nearest DVSS of IC in order to reduce the noise interference. Then it is possible to monitor the master clock that is generated internally from MCLKO, which is after all the monitor terminal, and hence does not guarantee drivability and phase-margin. Please tie the MCLKI terminal to DVSS when PLL is used. And please tie the PLLC terminal to DVSS when PLL is not used. Moreover, it is not necessary to set the ”PLLPDN” and “SMPR” when PLL is not used. 0 1 2 3 4 4 3 2 1 0 Lch Rch BCLK(64fs) SDTI LRCK(fs) 17:MSB, 0:LSB 17 16 Don’t Don’t Care 17 16 17 16 Don’t Care 0 1 2 3 6 7 8 9 10 0 1 2 Lch Rch BCLK(32fs) SDTI LRCLK(fs) 15:MSB, 0:LSB 15 14 13 12 11 0 1 2 3 6 7 8 9 10 15 14 13 12 11 15 14 13 0 1 2 3 4 11 14 15 16 17 0 1 2 17 16 15 14 11 4 3 2 0 1 Don’t Care Don’t Care Lch Rch BCLK(64fs) SDTI LRCLK(fs) 17:MSB, 0:LSB 0 1 2 3 4 11 12 13 14 15 0 1 2 15 14 13 12 11 4 3 2 0 1 Don’t Care Don’t Care Lch Rch BCLK(64fs) SDTI LRCLK(fs) 15:MSB, 0:LSB |
Аналогичный номер детали - BU7893GU |
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Аналогичное описание - BU7893GU |
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