1.

General description

The 74ABT841 high performance BiCMOS device combines low static and dynamic

power dissipation with high speed and high output drive.

The 74ABT841 bus interface register is designed to provide extra data width for wider

data/address paths of buses carrying parity.

The 74ABT841 consists of ten D-type latches with 3-state outputs. The flip-flops appear

transparent to the data when latch enable (LE) is HIGH. This allows asynchronous

operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW

transition, the data that meets the set-up and hold time is latched.

Data appears on the bus when the output enable (OE) is LOW. When OE is HIGH the

output is in the high-impedance state.

2.

Features and benefits

High speed parallel latches

Extra data width for wide address/data paths or buses carrying parity

Ideal where high speed, light loading, or increased fan-in are required with MOS

microprocessors

Broadside pinout

Output capability: +64 mA and

−32 mA

Power-up 3-state

Power-up reset

Latch-up protection exceeds 500 mA per JESD78B class II level A

ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

74ABT841

10-bit bus interface latch; 3-state

Rev. 03 — 25 March 2010

Product data sheet