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74AUP2G240GM датащи(PDF) 1 Page - NXP Semiconductors |
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74AUP2G240GM датащи(HTML) 1 Page - NXP Semiconductors |
1 / 20 page 1. General description The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A HIGH level at pin nOE causes the output to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input nOE is HIGH. 2. Features I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114E Class 3A exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Low static power consumption; ICC = 0.9 µA (maximum) I Latch-up performance exceeds 100 mA per JESD78 Class II I Inputs accept voltages up to 3.6 V I Low-noise overshoot and undershoot < 10 % of VCC I Input-disable feature allows floating input conditions I IOFF circuitry provides partial Power-down mode operation I Multiple package options I Specified from −40 °Cto+85 °C and −40 °C to +125 °C 74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Rev. 04 — 30 June 2009 Product data sheet |
Аналогичный номер детали - 74AUP2G240GM |
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Аналогичное описание - 74AUP2G240GM |
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