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ADC1115S125 датащи(PDF) 11 Page - NXP Semiconductors |
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ADC1115S125 датащи(HTML) 11 Page - NXP Semiconductors |
11 / 35 page ADC1115S125_1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 — 12 April 2010 11 of 35 NXP Semiconductors ADC1115S125 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 10.3 SPI timings [1] Typical values measured at VDDA(3V) =3V, VDDO = 1.8 V, VDDA(5V) =5V; Tamb =25 °C and CL =5pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) =3 V, VDDO = 1.8 V, VDDA(5V) =5V, VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified 11. Application information 11.1 Device control The ADC1115S125 can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up, and remains in this mode as long as pin CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as static control pins. SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been enabled, the device will remain in this mode. The transition from Pin control mode to SPI control mode is illustrated in Figure 7. Table 9. Characteristics Symbol Parameter Conditions Min Typ Max Unit SPI timings tw(SCLK) SCLK pulse width 40 - - ns tw(SCLKH) SCLK pulse width HIGH 16 - - ns tw(SCLKL) SCLK pulse width LOW 16 - - ns tsu set-up time data to SCLKH 5 - - ns CS to SCLKH 5 - - ns th hold time data to SCLKH 2 - - ns CS to SCLKH 2 - - ns fclk(max) maximum clock frequency - - 25 MHz Fig 6. SPI timing tsu SDIO SCLK R/W W1 W0 A12 A11 D2 D1 D0 tsu th th tw(SCLK) 005aaa065 CS tw(SCLKL) tw(SCLKH) |
Аналогичный номер детали - ADC1115S125 |
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Аналогичное описание - ADC1115S125 |
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