CS4223 CS4224

DS290F1

9

Notes: 10. After powering up the CS4223/4, PDN should be held low for 10 ms to allow the power supply to settle.

Parameter

Symbol

Min

Typ

Max

Unit

Audio ADC’s and DAC’s Sample Rate

Fs

4

-

50

kHz

XTI Frequency

XTI = 256, 384, or 512 Fs

1.024

-

26

MHz

XTI Pulse Width High

XTI = 512 Fs

XTI = 384 Fs

XTI = 256 Fs

13

21

31

-

-

-

-

-

-

ns

ns

ns

XTI Pulse Width Low

XTI = 512 Fs

XTI = 384 Fs

XTI = 256 Fs

13

21

31

-

-

-

-

-

-

ns

ns

ns

XTI Jitter Tolerance

-

500

-

psRMS

RST Low Time

(Note 10)

10

-

-

ms

SCLK falling edge to SDOUT output valid

DSCK = 0

--

ns

LRCK edge to MSB valid

--

45

ns

SDIN setup time before SCLK rising edge

DSCK = 0

25

-

-

ns

SDIN hold time after SCLK rising edge

DSCK = 0

25

-

-

ns

SCLK Period

--

ns

SCLK High Time

40

-

-

ns

SCLK Low Time

40

-

-

ns

SCLK rising to LRCK edge

DSCK = 0

35

-

-

ns

LRCK edge to SCLK rising

DSCK = 0

40

-

-

ns

1

(384) Fs

----------------------

20

+

1

(128) Fs

----------------------

sckh

sckl

sckw

t

t

t

MSB

MSB-1

*SCLK shown for DSCK = 0, SCLK inverted for DSCK = 1.

t dpd

SDOUT

LRCK

SCLK*

SDIN

dh

t

ds

t

lrpd

t

lrcks

t

lrckd

t

Figure 1. Serial Audio Port Data I/O Timing