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2009 ROHM Co., Ltd. All rights reserved.

2009.11 - Rev.A

Data Sheet

LSH2002-AA10A

(b) Data Output Timing Chart

After turning on the SP pulse, the analog output shape starts from the setting up point of 65 clock pulse.

Note) Output blank part cannot be used as the analog output standard level.

CLK

SP

Ao

1

2

52

53

54

64

65

66

Vdummy

Analog Output Period

1 to 52 pixels

53 to 64pixels

1 to 432pixels

Inner circuit

GND

SP

Vout

CLK

1

µF x 2

1

µF

432

200

Ω

75

Ω

1

µF

1

ANALOG MEMORY CIRCUIT

Peripheral circuit

87695

3

2

C3

C1

R1

R2

A

SP

CLK

GND

VLED

LED

BG

R

GND

14

C4

C2

∗ R1=R2=100Ω

C1=47

µF, C2=100pF

C3=100

µF, C4=0.1µF

∗ Please adjust the value of resistance to fit your interface circuit.