BU9883FV-W

Technical Note

9/18

www.rohm.com

2009.04 - Rev.B

© 2009 ROHM Co., Ltd. All rights reserved.

○

DEVICE ADDRESSING

・

Following a START condition, the master output the device address of the slave to be accessed.

The most significant four bits of the slave address are the “device type indentifier,” for this device, this is fixed as “1010.”

The next three bit specify a particular device. For PORT0 access, that are set “0”, “P1”, “P0”, for PORT 1～3 access, that

must be set “000”.

The last bit of the stream determines the operation to be performed.

When set to “1” a read operation is selected ; when set to “0,” a write operation is selected.

R/W set to “0” ･ ･ ･ ･ ･ ･ ･ ･ WRITE

R/W set to “1” ･ ･ ･ ･ ･ ･ ･ ･ READ

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ACKNOWLEDGE

・

Acknowledge is a software convention used to indicate successful data transfers.The master or the slave will release the

bus after transmitting eight bits.During the ninth clock cycle, the receiver will pull the SDA line LOW to Acknowledgethat

the eight bits of data has been received.

・

This device will respond with an Acknowledge after recognition of a START condition and its slave address.If both the

device and a write operation have been selected, this device will respond with an Acknowledge, after the receipt of each

subsequent 8-bit word.

・

In the READ mode, this device will transmit eight bit of data, release the SDA line, and monitor the line for an

Acknowledge.

・

If an Acknowledge is detected, and no STOP condition is generated by the master, this device will continue to transmit

the data.

・

If an Acknowledge is not detected, this device will terminate further data transmissions and await a STOP condition

before returning to the standby mode.

・

This device dosen't return Acknouwedge in internal write cycle.

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PORT0 access commands

○

For PORT0 access, WPB terminal must be set to “HIGH”.

○

This write commands operate EEPROM write sequence at address which is appointed by P1, P0. When the master

generates a STOP condition, this device begins the internal write cycle to the nonvolatile array.

Fig.41 ACKNOWLEDGE RESPONSE FROM RECEIVER

Fig.42 BYTE WRITE CYCLE TIMING (PORT0)

SDA

SCL

1

8

9

Acknowledge Signal

(ACK Signal)

START CONDITION

(START BIT)

（Fromμ-COM）

（IC OUTPUT DATA）

SDA

（μ-COM

OUTPUT DATA)

P1

0

WA7

1

1

0

0

W

R

I

T

E

S

T

A

R

T

R

/

W

1st WORD

ADDRESS(n)

SDA

LINE

SLAVE

ADDRESS

WA0

A

C

K

D7

DATA(n)

D0

A

C

K

S

T

O

P

P0

WPB