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ADM1033 датащи(PDF) 5 Page - ON Semiconductor |
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ADM1033 датащи(HTML) 5 Page - ON Semiconductor |
5 / 35 page ADM1033 http://onsemi.com 5 ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1) Parameter Unit Max Typ Min Test Conditions / Comments Tachometer Accuracy Fan Speed Measurement Accuracy ±4.0 % AGTL + INPUT (THERM) Input High Level 0.75 x REF V Input Low Level 0.4 V SERIAL BUS TIMING (Note 4) Clock Frequency, fSCLK See Figure 2 400 kHz Glitch Immunity, tSW See Figure 2 50 ns Bus Free Time, tBUF See Figure 2 1.3 ms Start Setup Time, tSU:STA See Figure 2 0.6 ms Start Hold Time, tHD:STA See Figure 2 0.6 ms Stop Condition Setup Time tSU:STO See Figure 2 0.6 ms SCL Low Time, tLOW See Figure 2 1.3 ms SCL High Time, tHIGH See Figure 2 0.6 ms SCL, SDA Rise Time, tr See Figure 2 1000 ns SCL, SDA Fall Time, tf See Figure 2 300 ns Data Setup Time, tSU:DAT See Figure 2 100 ns Detect Clock Low Timeout, tTIMEOUT See Note 5 25 35 ms 1. Typicals are at TA = 25°C and represent most likely parametric norm. Standby current typ. is measured with VCC = 3.3 V. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge. 2. Operation at 5.5 V is guaranteed by design, not production tested. 3. Recommend use of 100 kW pullup resistors for all open−drain outputs from the ADM1033. 4. Guaranteed by design, not production tested. 5. SMBus timeout disabled by default. See the SMBus section for more information. Figure 2. Serial Bus Timing Diagram P S tLOW tR tF tHD:STA tHD:DAT tSU:DAT tSU:STA tHD:STA tSU:STO tHIGH SCL PS SDA tBUF |
Аналогичный номер детали - ADM1033 |
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Аналогичное описание - ADM1033 |
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