CAT25010, CAT25020, CAT25040

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7

Write Status Register

The Status Register is written by sending a WRSR

instruction according to timing shown in Figure 7. Only bits

2 and 3 can be written using the WRSR command.

Write Protection

When WP input is low all write operations to the memory

array and Status Register are inhibited. WP going low while

CS is still low will interrupt a write to the status register. If

the internal write cycle has already been initiated, WP going

low will have no effect on any write operation to the Status

Register. The WP input timing is shown in Figure 8.

Figure 7. WRSR Timing

01

2

3

45

6

7

8

10

911

12

13

14

SCK

SI

MSB

HIGH IMPEDANCE

DATA IN

15

SO

7

6

5

4

3

2

10

00

0

0

0

0

0

1

OPCODE

Dashed Line = mode (1, 1)

CS

Figure 8. WP Timing

SCK

WP

Dashed Line = mode (1, 1)

WP

CS