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74AUP1G125DRLRG4 датащи(PDF) 2 Page - Texas Instruments |
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74AUP1G125DRLRG4 датащи(HTML) 2 Page - Texas Instruments |
2 / 24 page AUP LVC AUP AUP LVC Static-Power Consumption ( µA) Dynamic-Power Consumption (pF) † Single, dual, and triple gates 3.3-V Logic† 3.3-V Logic† 0% 20% 40% 60% 80% 100% 0% 20% 40% 60% 80% 100% −0.5 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 30 35 40 45 Time − ns † AUP1G08 data at CL = 15 pF Output Input Switching Characteristics at 25 MHz† SN74AUP1G125 SCES595J – JULY 2004 – REVISED MARCH 2010 www.ti.com This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Figure 1. AUP – The Lowest-Power Family Figure 2. Excellent Signal Integrity NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION(1) TOP-SIDE TA PACKAGE(2) ORDERABLE PART NUMBER MARKING(3) NanoStar™ – WCSP (DSBGA) Reel of 3000 SN74AUP1G125YFPR _ _ _ HM _ 0.23-mm Large Bump – YFP (Pb-free) NanoStar™ – WCSP (DSBGA) Reel of 3000 SN74AUP1G125YZPR _ _ _ HM _ 0.23-mm Large Bump – YZP (Pb-free) QFN – DRY Reel of 5000 SN74AUP1G125DRYR HM uQFN – DSF Reel of 5000 SN74AUP1G125DSFR HM –40°C to 85°C Reel of 3000 SN74AUP1G125DBVR SOT (SOT-23) – DBV H25_ Reel of 250 SN74AUP1G125DBVT Reel of 3000 SN74AUP1G125DCKR SOT (SC-70) – DCK HM_ Reel of 250 SN74AUP1G125DCKT SOT (SOT-553) – DRL Reel of 4000 SN74AUP1G125DRLR HM_ (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site. YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUTS OUTPUT Y OE A L H H L L L H X(1) Z (1) Floating inputs allowed. 2 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G125 |
Аналогичный номер детали - 74AUP1G125DRLRG4 |
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Аналогичное описание - 74AUP1G125DRLRG4 |
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