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TCA6416ZQSR датащи(PDF) 10 Page - Texas Instruments |
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TCA6416ZQSR датащи(HTML) 10 Page - Texas Instruments |
10 / 35 page Reset Input (RESET) Interrupt (INT)Output Bus Transactions Writes TCA6416 SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com The RESET input can be asserted to initialize the system while keeping the VCCP at its operating level. A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TCA6416 registers and I 2C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1), the I/O levels at the P port can be changed externally or through the master. This input requires a pullup resistor to VCCP, if no active connection is used. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting, data is read from the port that generated the interrupt or in a stop event. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input Port register. In the TCA6416, an interrupt is not immediately generated by any rising or falling edge of port inputs in input mode after issuing any I2C commands (read or write). In order to capture the INT in the TCA6416, the user needs to add one more SCL clock pulse after a Stop signal. The INT output has an open-drain structure and requires a pullup resistor to VCCP or VCCI depending on the application. If the INT signal is connected back to the processor that provides the SCL signal to the TCA6416, then the INT pin has to be connected to VCCI. If not, the INT pin can be connected to VCCP. Data is exchanged between the master and TCA6416 through write and read commands. Data is transmitted to the TCA6416 by sending the device address and setting the least-significant bit (LSB) to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one write transmission. The eight registers within the TCA6416 are configured to operate as four register pairs. The four pairs are input ports, output ports, polarity inversion ports and configuration ports. After sending data to one register, the next data byte is sent to the other register in the pair (see Figure 6 and Figure 7). For example, if the first byte is send to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers. 10 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 |
Аналогичный номер детали - TCA6416ZQSR |
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Аналогичное описание - TCA6416ZQSR |
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