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TL16C550DZQSR датащи(PDF) 9 Page - Texas Instruments

номер детали TL16C550DZQSR
подробное описание детали  ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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TL16C550DZQSR датащи(HTML) 9 Page - Texas Instruments

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TL16C550D
,, TL16C550DI
www.ti.com .................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008
TERMINAL FUNCTIONS (FOR PT/PFB PACKAGES) (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6
(RI) of the modem status register. Bit 2 (TERI) of the modem status register indicates that RI
RI
41
I
has transitioned from a low to a high level since the last read from the modem status
register. If the modem status interrupt is enabled when this transition occurs, an interrupt is
generated.
Request to send. When active, RTS informs the modem or data set that the ACE is ready to
receive data. RTS is set to the active level by setting the RTS modem control register bit and
RTS
32
O
is set to the inactive (high) level either as a result of a master reset or during loop mode
operations or by clearing bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS is set to the
inactive level by the receiver threshold control logic.
Receiver ready. Receiver direct memory access (DMA) signaling is available with RXRDY.
When operating in the FIFO mode, one of two types of DMA signaling can be selected using
the FIFO control register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA
mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made
between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are
made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or
RXRDY
29
O
FCR0 = 1, FCR3 = 0), when there is at least one character in the receiver FIFO or receiver
holding register, RXRDY is active (low). When RXRDY has been active but there are no
characters in the FIFO or holding register, RXRDY goes inactive (high). In DMA mode 1
(FCR0 = 1, FCR3 = 1), when the trigger level or the time-out has been reached, RXRDY
goes active (low); when it has been active but there are no more characters in the FIFO or
holding register, it goes inactive (high).
SIN
7
I
Serial data input. SIN is serial data input from a connected communications device.
Serial data output. SOUT is composite serial data output to a connected communication
SOUT
8
O
device. SOUT is set to the marking (high) level as a result of master reset.
Transmitter ready. Transmitter DMA signaling is available with TXRDY. When operating in
the FIFO mode, one of two types of DMA signaling can be selected using FCR3. When
operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports
TXRDY
23
O
single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports
multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO
has been filled.
VCC
42
2.25-V to 5.5-V power supply voltage
VSS
18
Supply common
Write inputs. When either WR1 or WR2 is active (low or high, respectively) and while the
WR1
16
ACE is selected, the CPU is allowed to write control words or data into a selected ACE
I
WR2
17
register. Only one of these inputs is required to transfer data during a write operation; the
other input must be tied to its inactive level (i.e., WR2 tied low or WR1 tied high).
XIN
14
External clock. XIN and XOUT connect the ACE to the main timing reference (clock or
I/O
XOUT
15
crystal).
Copyright © 2004–2008, Texas Instruments Incorporated
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