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TPS3808G50DBVRG4 датащи(PDF) 8 Page - Texas Instruments

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номер детали TPS3808G50DBVRG4
подробное описание детали  Low Quiescent Current, Programmable-Delay Supervisory Circuit
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

TPS3808G50DBVRG4 датащи(HTML) 8 Page - Texas Instruments

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DEVICE OPERATION
SENSE INPUT
RESET OUTPUT
V
IN
TPS3808G01
V
DD
SENSE
GND
RESET
R
1
R
2
1nF
V
=(1+)0.405
IT
¢
R1
R2
V
OUT
MANUAL RESET (MR) INPUT
2.5V
T PS 380 8G 25
O M AP 1510
V
DD
SENSE
V
DDSHV 1, 3, 6, 7, 9
GND
GND
C
T
MR
RESET
1M
RESPWRON
TPS3808
SBVS050J – MAY 2004 – REVISED AUGUST 2008 .......................................................................................................................................................... www.ti.com
supply line can be used to allow the reset signal for
The TPS3808 microprocessor supervisory product
the microprocessor to have a voltage higher than VDD
family is designed to assert a RESET signal when
(up to 6.5V). The pull-up resistor should be no
either the SENSE pin voltage drops below VIT or the
smaller than 10k
Ω as a result of the finite impedance
manual reset (MR) is driven low. The RESET output
of the RESET line.
remains asserted for a user-adjustable time after both
the manual reset (MR) and SENSE voltages return
above the respective thresholds. A broad range of
voltage threshold and reset delay time adjustments
The SENSE input provides a terminal at which any
are available, allowing these devices to be used in a
system voltage can be monitored. If the voltage on
wide array of applications. Reset threshold voltages
this pin drops below VIT, then RESET is asserted.
can be factory-set from 0.82V to 3.3V or from 4.4V to
The comparator has a built-in hysteresis to ensure
5.0V, while the TPS3808G01 can be set to any
smooth RESET assertions and de-assertions. It is
voltage above 0.405V using an external resistor
good analog design practice to put a 1nF to 10nF
divider.
Two
preset
delay
times
are
also
bypass capacitor on the SENSE input to reduce
user-selectable: connecting the CT pin to VDD results
sensitivity to transients and layout parasitics.
in a 300ms reset delay, while leaving the CT pin open
The TPS3808G01 can be used to monitor any
yields a 20ms reset delay. In addition, connecting a
voltage rail down to 0.405V using the circuit shown in
capacitor between CT and GND allows the designer
Figure 11.
to select any reset delay period from 1.25ms to 10s.
A typical application of the TPS3808G25 used with
the OMAP1510 processor is shown in Figure 10. The
open-drain RESET output is typically connected to
the RESET input of a microprocessor. A pull-up
resistor must be used to hold this line high when
RESET is not asserted. The RESET output is
undefined for voltage below 0.8V, but this is normally
not a problem since most microprocessors do not
function below this voltage. RESET remains high
(unasserted) as long as SENSE is above its threshold
Figure 11. Using the TPS3808G01 to Monitor a
(VIT) and the manual reset (MR) is logic high. If either
User-Defined Threshold Voltage
SENSE falls below VIT or MR is driven low, RESET is
asserted, driving the RESET pin to a low impedance.
The manual reset (MR) input allows a processor or
other logic circuits to initiate a reset. A logic low
(0.3VDD) on MR causes RESET to assert. After MR
returns to a logic high and SENSE is above its reset
threshold, RESET is de-asserted after the user
defined reset delay expires. Note that MR is internally
tied to VDD using a 90kΩ resistor so this pin can be
left unconnected if MR will not be used.
See Figure 12 for how MR can be used to monitor
multiple system voltages. Note that if the logic signal
driving MR does not go fully to VDD, there will be
Figure 10. Typical Application of the TPS3808
with an OMAP Processor
some additional current draw into VDD as a result of
the internal pull-up resistor on MR. To minimize
current draw, a logic-level FET can be used as
Once MR is again logic high and SENSE is above VIT
illustrated in Figure 13.
+ VHYS (the threshold hysteresis), a delay circuit is
enabled which holds RESET low for a specified reset
delay period. Once the reset delay has expired, the
RESET pin goes to a high impedance state. The
pull-up resistor from the open-drain RESET to the
8
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Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS3808


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