8

Standard ICs

BU9729K

(6) Reset

1

10

∗

LSB

MSB

∗∗∗∗

This command should be executed after the power supply has been turned on and before any other command is

executed. This command causes the BU9729K to initialize the following:

Display Off

Address Counter Reset

(1) Register

The BU9729K has an 8-bit command / data register. Serial data is read in 8-clock units of SCK.

If the data read into the register is displayed data (C / D is LOW at the eighth clock of SCK), it is written to the

DDRAM. If it is command data (C / D is HIGH at the eighth clock of SCK), it is output to the command decoder to

control the BU9729K.

(2) Address counter

The address counter indicates DDRAM addresses. When the Address Set command is written to a command or data

register, the address data is sent automatically to the address counter.

After data has been written to the DDRAM, the address counter increments automatically by either + 1 or + 2. The

amount by which the counter increments is determined automatically, based on the following status.

DDRAM 8-bit writing (C / D is LOW at the eighth clock of SCK)

→ + 2

DDRAM 4-bit writing (C / D is HIGH at the eighth clock of SCK)

→ + 1

When the address counter has counted to the address 11H, it becomes 00H the next time it is incremented.

(3) Display data RAM (DDRAM)

The display data RAM (DDRAM) is used to store display data. It has a capacity of 18 addresses

× 4 bits.

The relationship between the DDRAM and the display position is shown below.

DD RAM address

00

11

10

0F

01

02

03

04

05

06

07

·········

1

2

3

0

COM2

COM3

COM4

COM1