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KM416C256D датащи(PDF) 1 Page - Samsung semiconductor

номер детали KM416C256D
подробное описание детали  256K x 16Bit CMOS Dynamic RAM with Fast Page Mode
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производитель  SAMSUNG [Samsung semiconductor]
домашняя страница  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM416C256D датащи(HTML) 1 Page - Samsung semiconductor

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KM416C256D, KM416V256D
CMOS DRAM
This is a family of 262,144 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5.0V or +3.3V), access time (-5,-6,-7), power consumption(Normal or Low power) and
package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and
Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 256Kx16 fast page mode DRAM family is
fabricated using Samsung's advanced CMOS process to realize high band-width, low power consumption and high reliability.
It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
¡Ü
Part Identification
- KM416C256D/DL (5V, 512K Ref.)
- KM416V256D/DL (3.3V, 512K Ref.)
¡Ü
Fast Page Mode operation
¡Ü
2 CAS Byte/Wrod Read/Write operation
¡Ü
CAS-before-RAS refresh capability
¡Ü
RAS-only and Hidden refresh capability
¡Ü
Self-refresh capability (L-ver only)
¡Ü
TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
¡Ü
Early Write or output enable controlled write
¡Ü
JEDEC Standard pinout
¡Ü
Available in 40-pin SOJ 400mil and44(40)-pin
TSOP(II) 400mil packages
¡Ü
Triple +5V¡¾10% power supply(5V product)
¡Ü
Triple +3.3V¡¾0.3V power supply(3.3V product)
Control
Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Column Decoder
Lower
Data out
Buffer
RAS
UCAS
LCAS
W
Vcc
Vss
DQ0
to
DQ7
A0
.
.
A8
Memory Array
262,144 x16
Cells
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
256K x 16Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
¡Ü
Refresh Cycles
Part
NO.
VCC
Refresh
cycle
Refresh period
Normal
L-ver
C256D
5V
512K
8ms
128ms
V256D
3.3V
¡Ü
Performance Range:
Speed
tRAC
tCAC
tRC
tPC
Remark
-5
50ns
15ns
90ns
35ns
5V only
-6
60ns
15ns
10ns
40ns
5V/3.3V
-7
70ns
20ns
130ns
45ns
5V/3.3V
¡Ü
Active Power Dissipation
Speed
3.3V(512 Ref.)
5V(512 Ref.)
-5
-
605
-6
325
495
-7
290
440
Unit : mW
Upper
Data in
Buffer
Upper
Data out
Buffer
Lower
Data in
Buffer
DQ8
to
DQ15
OE


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