поискавой системы для электроныых деталей |
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KM432S2030CT-F7 датащи(PDF) 8 Page - Samsung semiconductor |
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KM432S2030CT-F7 датащи(HTML) 8 Page - Samsung semiconductor |
8 / 43 page KM432S2030C CMOS SDRAM REV. 1.1 Mar. '99 - 8 - 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Note : AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol -6 -7 -8 -10 Unit Note Min Max Min Max Min Max Min Max CLK cycle time CAS Latency=3 tCC 6 1000 7 1000 8 1000 10 1000 ns 1 CAS Latency=2 - - 10 12 CLK to valid output delay CAS Latency=3 tSAC - 5.5 - 5.5 - 6 - 7 ns 1, 2 CAS Latency=2 - - - - - 7 - 8 Output data tOH 2.5 - 2.5 - 2.5 - 2.5 - ns 2 CLK high pulse width CAS Latency=3 tCH 2.5 - 3 - 3 - 3.5 - ns 3 CAS Latency=2 - CLK low pulse width CAS Latency=3 tCL 2.5 - 3 - 3 - 3.5 - ns 3 CAS Latency=2 - Input setup time CAS Latency=3 tSS 1.5 - 1.75 - 2 - 2.5 - ns 3 CAS Latency=2 - - Input hold time tSH 1 - 1 - 1 - 1 - ns 3 CLK to output in Low-Z tSLZ 1 - 1 - 1 - 1 - ns 2 CLK to output in Hi-Z CAS Latency=3 tSHZ - 5.5 - 5.5 - 6 - 7 ns CAS Latency=2 - - - - - 7 - 8 Symbol Version Unit -6 -7 -8 -10 CL 3 - 3 - 3 2 3 2 CLK tCC(min) 6 - 7 - 8 10 10 12 ns tRRD(min) 2 CLK tRCD(min) 3 - 3 - 3 2 2 2 CLK tRP(min) 3 - 3 - 3 2 2 2 CLK tRAS(min) 7 - 7 - 6 5 5 4 CLK tRAS(max) 100 us tRC(min) 11 - 10 - 9 7 7 6 CLK 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV" |
Аналогичный номер детали - KM432S2030CT-F7 |
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Аналогичное описание - KM432S2030CT-F7 |
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