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KM68512B датащи(PDF) 5 Page - Samsung semiconductor |
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KM68512B датащи(HTML) 5 Page - Samsung semiconductor |
5 / 9 page Revision 0.0 KM68512B Family CMOS SRAM January 1998 5 Advance AC CHARACTERISTICS (Vcc=4.5~5.5V, KM68512B Family : TA=0 to 70°C, KM68512BI Family : TA=-40 to 85°C) Parameter List Symbol Speed Bins Units 55ns 70ns Min Max Min Max Read Read cycle time tRC 55 - 70 - ns Address access time tAA - 55 - 70 ns Chip select to output tCO - 55 - 70 ns Output enable to valid output tOE - 25 - 35 ns Chip select to low-Z output tLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - ns Chip disable to high-Z output tHZ 0 20 0 25 ns Output disable to high-Z output tOHZ 0 20 0 25 ns Output hold from address change tOH 10 - 10 - ns Write Write cycle time tWC 55 - 70 - ns Chip select to end of write tCW 45 - 60 - ns Address set-up time tAS 0 - 0 - ns Address valid to end of write tAW 45 - 60 - ns Write pulse width tWP 40 - 55 - ns Write recovery time tWR 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 ns Data to write time overlap tDW 20 - 30 - ns Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns CL1) 1. Including scope and jig capacitance AC OPERATING CONDITIONS TEST CONDITIONS ( Test Load and Input/Output Reference) Input pulse level : 0.8 to 2.4V Input rising and faling time : 5ns Input and output reference voltage :1.5V Output load(see right) : C L=100pF+1TTL DATA RETENTION CHARACTERISTICS 1. CS1 ≥Vcc-0.2V, CS2≥Vcc-0.2V( CS1 controlled) or CS2≤0.2V(CS2 controlled). Item Symbol Test Condition Min Typ Max Unit Vcc for data retention VDR CS11) ≥Vcc-0.2V 2.0 - 5.5 V Data retention current IDR Vcc=3.0V, CS1 ≥Vcc-0.2V KM68512BL-L - 0.5 10 µA KM68512BLI-L - - 15 Data retention set-up time tSDR See data retention waveform 0 - - ms Recovery time tRDR 5 - - |
Аналогичный номер детали - KM68512B |
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Аналогичное описание - KM68512B |
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