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KM6164002E датащи(PDF) 4 Page - Samsung semiconductor |
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KM6164002E датащи(HTML) 4 Page - Samsung semiconductor |
4 / 9 page KM6164002, KM6164002E, KM6164002I CMOS SRAM PRELIMINARY Rev 2.0 - 6 - June -1997 TIMING WAVE FORM OF READ CYCLE(2)(WE=VIH) CS OE Data Out Data Valid ADD NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL Levels. 4. At any given temperature and voltage condition, t HZ(Max.) is less than t LZ (Min.) both for a given device and from device to device. 5. Transition is measured ±200§Æ from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. UB, LB UB, LB TIMING WAVE FORM OF WRITE CYCLE(1)(OE=Clock) OE CS Data In WE High-Z ADD Data Out Data Valid High-Z(8) tRC tAA tCO tBLZ(4,5) tOE tBA tOLZ tLZ(4,5) tHZ(3,4,5) tBHZ(3,4,5) tOHZ tOH tWC tAW tWP(2) tBW tCW(3) tAS(4) tOHZ(6) tDW tDH tWR(5) |
Аналогичный номер детали - KM6164002E |
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Аналогичное описание - KM6164002E |
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