поискавой системы для электроныых деталей |
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TPS2493PW датащи(PDF) 6 Page - Texas Instruments |
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TPS2493PW датащи(HTML) 6 Page - Texas Instruments |
6 / 33 page UVEN 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VREF PROG TIMER OV IMON GND VCC SENSE GATE OUT NC FLT PG PW PACKAGE (top view) TPS2492 TPS2493 SLUSA65A – JULY 2010 – REVISED AUGUST 2010 www.ti.com TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. UVEN 1 I A low input inhibits GATE. A logic input can drive this pin as an enable. VREF 2 O 4-V reference voltage used to set the power threshold on PROG pin. PROG 3 I FET power-limit programming pin TIMER 4 I/O A capacitor from TIMER to ground sets the fault timer period. OV 5 I Overvoltage sensing input. A high input inhibits GATE. IMON 6 O Current monitor output, nominally VIMON = 48 x (VVCC-SENSE). GND 7 PWR Ground PG 8 O Active low power good output. This is driven by VVCC-SENSE. Active low fault indicator output. FLT indicates the fault timer has expired. FLT is FLT 9 O reset by UVEN, UVLO, or automatic restart. NC 10 No connect FET source voltage (output) sensing pin. Gate is clamped to a diode drop below OUT 11 I OUT. GATE 12 O Gate driver output for external FET. Current sensed as VVCC-SENSE and the FET VDS as VSENSE-OUT. For low FET VDS, SENSE 13 I current limits at 50mV. VCC 14 I Input supply and current sense positive input 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 |
Аналогичный номер детали - TPS2493PW |
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Аналогичное описание - TPS2493PW |
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