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ISL6123IRZA датащи(PDF) 8 Page - Intersil Corporation

номер детали ISL6123IRZA
подробное описание детали  Power Sequencing Controllers
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производитель  INTERSIL [Intersil Corporation]
домашняя страница  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL6123IRZA датащи(HTML) 8 Page - Intersil Corporation

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ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
8
FN9005.11
August 25, 2011
Once all four UVLO inputs and ENABLE are satisfied for 10ms,
the four DLY_ON capacitors are simultaneously charged with
1µA current sources to the DLY_Vth level of 1.27V. As each
DLY_ON pin reaches the DLY_Vth level, its associated GATE
turns on, with a 1µA source current to the VQP voltage of VDD
+ 5.3V. Thus, all four GATEs sequentially turn on. Once at
DLY_Vth, the DLY_ON pins discharge so they are ready when
next needed.
After the entire turn-on sequence has been completed and all
GATEs have reached the charge pumped voltage (VQP), a
160ms delay is started to ensure stability, after which the
RESET output is released to go high. After turn-on, if any input
falls below its UVLO point for longer than the glitch filter
period (~30µs), it is considered a fault. RESET and SYSRST
are pulled low, and all GATEs are simultaneously also pulled
low. In this mode, the GATEs are pulled low with 88mA.
Normal shutdown mode is entered when no UVLO is violated
and ENABLE is deasserted. When ENABLE is deasserted,
RESET is asserted and pulled low. Next, all four shutdown
ramp capacitors on the DLY_OFF pins are charged with a 1µA
source. When any ramp-capacitor reaches DLY_Vth, a latch is
set, and a current is sunk on the respective GATE pin to turn
off its external MOSFET. When the GATE voltage is
approximately 0.6V, the GATE is pulled down the rest of the
way at a higher current level. Each individual external FET is
thus turned off, which removes the voltages from the load in
the programmed sequence.
The ISL6123 and ISL6124 have the same functionality,
except for the ENABLE active polarity; the ISL6124 has an
ENABLE input. Additionally, the ISL6123 and ISL6130 also
have an ultra low-power sleep state when ENABLE is low.
The ISL6125 has the same personality as the ISL6124, but
instead of charged-pump-driven GATE outputs, it has
open-drain outputs that can be pulled up to a maximum of
VDD.
The ISL6126 and ISL6130 are different in that their on
sequence is not time determined but voltage determined.
Each of the four channels operates independently. Once the
IC is biased and any one of the UVLO inputs is greater than
the 0.63V internal reference, the ENABLE input is also
satisfied. The GATE for the associated UVLO input turns on.
In turn, the other UVLO inputs must be satisfied for the
associated GATEs to turn on. For a period of 150ms after all
GATEs are fully on (GATE voltage = VQP), RESET is released to
go high. The UVLO inputs can be driven by either a previously
turned-on output rail offering a voltage-determined sequence
or by logic signal inputs. Any subsequent UVLO level that is
less than its programmed level pulls the associated GATE and
RESET output low (if previously released) but does not
latch-off the other GATEs. Predetermined turn-off is
accomplished by deasserting ENABLE. This causes RESET to
latch low and all four GATE outputs to follow the programmed
turn-off sequence, similarly to the ISL6124.
The ISL6127 is a 4-channel sequencer pre-programmed for
A-B-C-D turn-on and D-C-B-A turn-off. After all four UVLO and
ENABLE inputs are satisfied for ~10ms, the sequencing
starts. The next GATE in the sequence starts to ramp up once
the previous GATE has reached ~VQP-1V. After a period of
160ms after the last GATE is at VQP, the RESET output is
deasserted. If any UVLO is unsatisfied, RESET is pulled low,
SYSRST is pulled low, and all GATEs are simultaneously
turned off. When ENABLE is signaled high, the D GATE starts
to pull low. Once below 0.6V, the next GATE starts to pull low,
and so on, until all GATEs are at 0V. Unloaded, this turn-off
sequence completes in <1ms.
This variant offers a lower cost and size implementation
because the external delay capacitors are not used. Because
the delay capacitors are not used, this IC cannot delay the
start of subsequent GATEs. Thus, necessary stabilization or
system housekeeping need to be considered.
The ISL6128 is a 4-channel device that groups the four
channels into two groups of two channels each. Each group
of A, B and C, D, has its own ENABLE and RESET I/O pins. All
four UVLO and both ENABLEs must be satisfied for
sequencing to start. The A, B group turns on first, 10ms after
the second ENABLE is pulled low, with A then B turning on,
followed by C then D.
Once the preceding GATE = VQP, the next DLY_ON pin starts to
charge its capacitor; thus, all four GATEs turn on. Approximately
160ms after D GATE = VQP, the RESET output is released to go
high. Once any UVLO is unsatisfied, only the related group’s
RESET and two GATEs are pulled low. The related EN input must
be cycled for the faulted group to be turned on again.
Normal shutdown is invoked by signaling both ENABLE inputs
high, which causes the two related GATEs to shut down in
reverse order from turn-on. DLY_X capacitors adjust the delay
between GATES during turn-on and turn-off, but not the order.
During bias up, the RESET output is guaranteed to be in the
correct state, with VDD lower than 1V.
Upon power-up, the SYSRST pin follows VDD with a weak
internal pull-up. It is both an input and an output connection and
can provide two functions. As an input, if it is pulled low, all
GATEs are unconditionally shut off, and RESET pulls low
(Figure 8). This input can also be used as a no-wait enabling
input. If all inputs (ENABLE and UVLO) are satisfied, it does not
wait through the ~10ms enable delay to initiate DLY_ON
capacitor charging when released to go high. As an output, it is
useful when implementing multiple sequencers in a design
needing simultaneous shutdown, as with a kill switch across all
sequencers. Once any UVLO is unsatisfied longer than tFIL, the
related SYSRST pulls low. It also pulls low all other SYSRST
inputs that are on a common connection. By doing so, it
unconditionally shuts down all outputs across multiple
sequencers.
Except for the ISL6128 after a fault, restart of the turn-on
sequence is automatic, once all requirements are met. This
allows for no interaction between the sequencer and a controller
IC, if desired. The ENABLE and RESET I/O do allow for a higher
level of feedback and control, if desired. The ISL6128 requires
that the related ENABLE be cycled for restart of its associated
group GATEs. If no capacitors are connected between DLY_ON or
DLY_OFF pins and ground, then all such related GATEs start to
turn on immediately after the 10ms (TUVLOdel) ENABLE
stabilization timeout has expired. The GATEs start to turn off
immediately when ENABLE is asserted.


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