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ADC11C125HFEB датащи(PDF) 4 Page - National Semiconductor (TI) |
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ADC11C125HFEB датащи(HTML) 4 Page - National Semiconductor (TI) |
4 / 24 page Pin No. Symbol Equivalent Circuit Description 11 CLK+ The clock input pins can be configured to accept either a single- ended or a differential clock input signal. When the single-ended clock mode is selected through CLK_SEL/ DF (pin 8), connect the clock input signal to the CLK+ pin and connect the CLK− pin to AGND. When the differential clock mode is selected through CLK_SEL/DF (pin 8), connect the positive and negative clock inputs to the CLK + and CLK− pins, respectively. The analog input is sampled on the falling edge of the clock input. 12 CLK− DIGITAL I/O 20-24, 27-32 D0–D10 Digital data output pins that make up the 10-Bit conversion result. D0 (pin 20) is the LSB, while D10 (pin 32) is the MSB of the output word. Output levels are CMOS compatible. 33 OVR Over-Range Indicator. This output is set HIGH when the input amplitude exceeds the 11-Bit conversion range (0 to 2047). 34 DRDY Data Ready Strobe. This pin is used to clock the output data. It has the same frequency as the sampling clock. One word of data is output in each cycle of this signal. The rising edge of this signal should be used to capture the output data. 17-19 OGND Output GND, internally tied to GND through 5k ohm resistor to provide pin compatibility with 14 and 12 bit ADCs. ANALOG POWER 1, 6, 9, 37, 40, 41, 48 V A Positive analog supply pins. These pins should be connected to a quiet +3.3V source and be bypassed to AGND with 0.01 µF and 0.1 µF capacitors located close to the power pins. 2, 5, 10, 38, 39, 42, 47, Exposed Pad AGND The ground return for the analog supply. Note: Exposed pad on bottom of package must be soldered to ground plane to ensure rated performance. DIGITAL POWER 13 V D Positive digital supply pin. This pin should be connected to a quiet +3.3V source and be bypassed to DGND with a 0.01 µF and 0.1 µF capacitor located close to the power pin. 14 DGND The ground return for the digital supply. 15, 25, 36 V DR Positive driver supply pin for the output drivers. This pin should be connected to a quiet voltage source of +1.8V and be bypassed to DRGND with 0.01 µF and 0.1 µF capacitors located close to the power pins. 16, 26, 35 DRGND The ground return for the digital output driver supply. These pins should be connected to the system digital ground, but not be connected in close proximity to the ADC's DGND or AGND pins. See Section 6.0 (Layout and Grounding) for more details. www.national.com 4 |
Аналогичный номер детали - ADC11C125HFEB |
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Аналогичное описание - ADC11C125HFEB |
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