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TDA19977A датащи(PDF) 2 Page - NXP Semiconductors

номер детали TDA19977A
подробное описание детали  Triple input HDMI 1.4a compliant receiver interface with equalizer
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

TDA19977A датащи(HTML) 2 Page - NXP Semiconductors

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TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
2 of 40
NXP Semiconductors
TDA19977A; TDA19977B
Triple input HDMI receiver interface with digital processing
2.
Features and benefits
Complies with the HDMI 1.4a, DVI 1.0, CEA-861-D and HDCP (TDA19977A only)
1.4 standards
Three independent HDMI inputs, up to the HDMI frequency of 205 MHz
Embedded auto-adaptive equalizer on all HDMI links
EDID memory: 253 shared bytes and three bytes dedicated to each HDMI input
Supports color depth processing (8-bit, 10-bit or 12-bit per color)
Color gamut metadata packet with interrupt on each update, readable via the I2C-bus
Up to four S/PDIF or I2S-bus outputs (eight channels) at a sampling rate up to 192 kHz
with IEC 60958/IEC 61937 stream
HBR audio stream up to 768 kHz with four demultiplexed S/PDIF or I2S-bus outputs
HBR streams (compatible with DTS-HD master audio and Dolby TrueHD up to eight
channels due to HBR packet for stream with a frame rate up to 768 kHz) support
DSD and DST audio stream up to six DSD channels output for SACD with DST audio
packet support
Channel status decoder supports multi-channel reception
Improved audio clock generation using an external reference clock
System/master clock output (128/256/512
× f
s) enables the use of the UDA1334BTS
The HDMI interface supports:
All HDTV formats up to 1920
× 1080p at 50/60 Hz and WUXGA (1920 × 1200p at
60 Hz) with support for reduced blanking
3D formats including all primary formats up to 1920
× 1080p at 30 Hz Frame
Packing and 1920
× 1080p at 60 Hz Top-and-Bottom
PC formats up to UXGA (1600
× 1200p at 60 Hz)
Embedded oscillator (an external crystal can be used)
Frame and field detection for interlaced video signal
Sync timing measurements for format recognition
Improved system for measurements of blanking and video active area allowing an
accurate recognition of PC and TV formats
HDCP (TDA19977A only) with repeater capability
Embedded non-volatile memory storage of HDCP (TDA19977A only) keys
Programmable color space input signal conversion from RGB-to-YCbCr or
YCbCr-to-RGB
Output formats: RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 semi-planar based on the
ITU-R BT.601 standard and YCbCr 4:2:2 ITU-R BT.656
8-bit, 10-bit or 12-bit output formats selectable using the I2C-bus (8-bit and 10-bit only
in 4:4:4 format)
I2C-bus adjustable timing of video port (tsu(Q) and th(Q))
Downsampling-by-two with selectable filters on Cb and Cr channels in 4:2:2 mode
Internal video and audio pattern generator
Controllable using the I2C-bus; 5 V tolerant and bit rate up to 400 kbit/s
DDC-bus inputs 5 V tolerant and bit rate up to 400 kbit/s
LV-TTL outputs
Power-down mode
CMOS process


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