74LVC1G125

SINGLE BUFFER GATE WITH 3-STATE OUTPUT

74LVC1G125

Document number: DS32202 Rev. 2 - 2

8 of 14

www.diodes.com

October 2010

© Diodes Incorporated

(see Note A)

From Output

Under Test

Open

GND

S1

TEST

S1

Open

Vload

GND

Vcc

Inputs

V

∆

1.8V±0.15V

≤2ns

30pF

1K

Ω

0.15V

2.5V±0.2V

≤2ns

30pF

500

Ω

0.15V

3.3V±0.3V

3V

≤2.5ns

1.5V

6V

50pF

500

Ω

0.3V

5V±0.5V

≤2.5ns

50pF

500

Ω

0.3V

Voltage Waveform Pulse Duration

Voltage Waveform Enable and Disable Times

Low and High Level Enabling

Voltage Waveform Propagation Delay Times

Inverting and Non Inverting Outputs

Figure 2. Load Circuit and Voltage Waveforms

Notes:

A. Includes test lead and test apparatus capacitance.

B. All pulses are supplied at pulse repetition rate

≤ 10 MHz.

C. Inputs are measured separately one transition per measurement.