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FAN9612 датащи(PDF) 6 Page - Fairchild Semiconductor

номер детали FAN9612
подробное описание детали  Design Consideration for Interleaved Boundary Conduction Mode PFC
Download  18 Pages
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производитель  FAIRCHILD [Fairchild Semiconductor]
домашняя страница  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

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AN-6086
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.4 • 4/22/10
6
1
OUT
AUX
ZCD
BOOST
VN
R
mA N
>⋅
(9)
For low-power applications, such as adaptors, the supply
voltage (VDD) for FAN9611/12 is supplied by auxiliary
winding of inductor, as shown in Figure 10. Since the
auxiliary winding voltage varies extensively within half of
line cycle, DC blocking capacitor (CB) is used to guarantee
stable VDD voltage.
When supplying VDD using the auxiliary winding, the turns
ratio should be determined as:
2
BOOST
OUT
AUX
Z
NV
N
N
V
=≅
(10)
where VZ is the Zener diode voltage for VDD.
The reason for setting the turns ratio such that peak-to-peak
voltage of auxiliary winding is around twice of VZ is to
guarantee stable VDD supply without under-voltage lockout
(UVLO) during startup.
AUX
OUT
BOOST
N
V
N
(( ))
AUX
OUT
IN
BOOST
N
VV
t
N
()
AUX
IN
BOOST
N
Vt
N
Figure 10. VDD Supply Circuit using Auxiliary Winding
The average current through the startup resistor should be
larger than the startup current (100
μA), determined as:
,
22
100
LINE MIN
START
START
V
I
A
R
μ
π
=>
(11)
The startup resistor also should be determined by
considering the minimum startup time, which is given as:
,
22
(
100
)
ON
DD
START
LINE MIN
START
VC
t
V
A
R
μ
π
=
(12)
where
VON is UVLO start voltage for VDD and
CDD is the total capacitance of capacitors connected to the
VDD pin.
Typically 20~50
μF of electrolytic capacitor (C
VDD2) is used
together with 2~4
μF of bypass capacitor (C
VDD1).
The power consumption in the startup resistor is obtained as:
2
,
LINE MAX
LOSS
START
V
P
R
=
(13)
(Design Example)
Selecting the turns ratio of the
inductor (NBOOST/NAUX) as 10, NAUX is obtained as 3 and
the value of RZCD is given as:
400
3
40
11
30
OUT
AUX
ZCD
BOOST
VN
R
k
mA N
mA
>⋅
=
=
Ω
RZCD is selected as 47kΩ.
Assuming that VDD is supplied from auxiliary power
supply, VDD supply circuit using the auxiliary winding is
not included in this example.
[STEP-3] Design VIN Sense Circuit
Since the RMS value of AC line voltage is directly
proportional to the peak of the line voltage, FAN9611/12
detects the peak value of input voltage to sense the RMS
value of the line voltage, which permits a simple voltage
divider for line voltage sensing, as shown in Figure 11. The
detected line voltage information is used for line under-
voltage lockout (UVLO), and line feed-forward for PWM
control.
When the peak of VIN pin voltage drops below 0.95V, the
line UVLO (brownout protection) is triggered and
FAN9611/12 stops operating. The RMS value of the line
voltage that causes line UVLO is given as:
12
.
2
0.95
(
)
2
IN
IN
LINE UVLO
AC
IN
RR
VV
R
+
=⋅
(14)
The internal switched current source allows UVLO
hysteresis on line voltage as:
1
1,
2
,
(1)
2
2
IN
IN
IN HYS
IN
LINE HYS
R
RR
R
VA
μ
++
=⋅
(
VAC )
(15)
From Equation 15, RIN,HYS with a given hysteresis of line
voltage is obtained as:
.2
,1
12
2
()
2
LINE HYS
IN
IN HYS
IN
IN
IN
VR
RR
AR
R
μ
=−
+
(16)


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