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FAN5026 датащи(PDF) 11 Page - Fairchild Semiconductor |
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FAN5026 датащи(HTML) 11 Page - Fairchild Semiconductor |
11 / 17 page © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5026 • Rev. 1.0.8 11 Duty Cycle Clamp During severe load increase, the error amplifier output can go to its upper limit, pushing a duty cycle to almost 100% for significant amount of time. This could cause a large increase of the inductor current and lead to a long recovery from a transient, over-current condition, or even to a failure at especially high input voltages. To prevent this, the output of the error amplifier is clamped to a fixed value after two clock cycles if severe output voltage excursion is detected, limiting the maximum duty cycle to: + = IN V 4 . 2 V V DC IN OUT MAX (5) This is designed to not interfere with normal PWM operation. When FPWM is grounded, the duty cycle clamp is disabled and the maximum duty cycle is 87%. Figure 12. Current Limit / Summing Circuits Gate Driver Section The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals, providing necessary amplification, level shifting, and shoot-through protection. Also, it has functions that optimize the IC performance over a wide range of operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1V. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1V. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction or shoot-through. There must be a low-resistance, low-inductance path between the driver pin and the MOSFET gate for the adaptive dead-time circuit to function properly. Any delay along that path subtracts from the delay generated by the adaptive dead-time circuit and shoot- through may occur. Frequency Loop Compensation Due to the implemented current-mode control, the modulator has a single-pole response with -1 slope at frequency determined by load: O O PO C R 2 1 f π = (6) where RO is load resistance; CO is load capacitance. |
Аналогичный номер детали - FAN5026 |
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Аналогичное описание - FAN5026 |
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